Discover chipsalliance/i3c-core Open Source project

3,806

rocket-chip

Rocket Chip Generator

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

3,077

verible

C++

1,290

riscv-dv

Random instruction generator for RISC-V processor verification

Cores-VeeR-EH1

firrtl

Flexible Intermediate Representation for RTL

A template project for beginning new Chisel work

704

chisel-template

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

551

Surelog

f4pga

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Example designs showing different ways to use F4PGA toolchains.

284

f4pga-examples

Cores-VeeR-EL2

dromajo

RISC-V RV64GC emulator designed for RTL co-simulation

Cores-VeeR-EH2

UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

silicon-notebooks

treadle

Chisel/Firrtl execution engine

SystemVerilog support for Yosys

151

synlig

Advanced Interface Bus (AIB) die-to-die hardware open source

148

aib-phy-hardware

VeeR-ISS

Caliptra

Caliptra IP and firmware for integrated Root of Trust block

107

FPGA tool performance profiling

106

fpga-tool-perf

FPGA Assembly (FASM) Parser and Generator

101

fasm

Plugins for Yosys developed as part of the F4PGA project.

yosys-f4pga-plugins

OmniXtend cache coherence protocol

omnixtend

playground

uvm-verilator

caliptra-rtl

HW Design Collateral for Caliptra RoT IP

Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

caliptra-sw

Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)

fpga-interchange-schema

Cap'n Proto

rocket-tools

Shell

riscv-vector-tests

Unit tests generator for RVV 1.0

AIB-specification

Home of the Advanced Interface Bus (AIB) specification.

cde

A Scala library for Context-Dependent Environments

Python interface to FPGA interchange format

python-fpga-interchange

The specification for the FIRRTL language

Cores-SweRV_fpga

Tcl

firrtl-spec

TeX

espresso

UHDM-integration-tests

Python library for working Standard Delay Format (SDF) Timing Annotation files.

f4pga-sdf-timing

AIB Generator: Analog hardware compiler for AIB PHY

aib-phy-generator

Shell

verible-linter-action

Automatic SystemVerilog linting in github actions with the help of Verible

SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...

riscv-fw-infrastructure

aib-protocols

tilelink

Intel Compiler for SystemC

systemc-compiler

C++

ideas

f4pga-xc7-bram-patch

Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.

LLVM

caliptra-dpe

High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

diplomacy

An RTL generator for a last-level shared inclusive TileLink cache controller

homebrew-verible

Ruby

rocket-chip-inclusive-cache

Processor support packages

Cores-SweRV-Support-Package

Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards

rocket-chip-fpga-shells

The working draft to split rocket core out from rocket chip

rocket

RTL blocks compatible with the Rocket Chip Generator

rocket-chip-blocks

Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

tools-cocotb-verilator-build

Makefile

OmnixtendEndpoint

Bluespec

f4pga-bitstream-viewer

Tool for graphically viewing FPGA bitstream files and their connection to FASM features.

The 'missing header' for Chisel

chisel-interface

Library to convert a FASM file into BELs importable into Vivado.

f4pga-xc-fasm2bels

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

foundation

f4pga-v2x

Repository to run extensive tests on the FPGA interchange format

fpga-interchange-tests

FIRRTL grammar for tree-sitter

tree-sitter-firrtl

C++

verible-formatter-action

PCB libraries and templates for rocket-chip based FPGA/ASIC designs

rocket-pcb

CHIPS Alliance Technical Advisory Council

f4pga-database-visualizer

JavaScript

tac

caliptra-ureg

f4pga-xc-fasm

Output of the sv-tests runs.

sv-tests-results

HTML

rvdecoderdb

The Scala parser to parse riscv/riscv-opcodes generate

Collection of Routing Resources Graph (RR Graph) libraries for VPR

chips-alliance-website

SCSS

f4pga-rr-graph

TextMate-compatible description of FIRRTL syntax for use with GitHub's Linguist

vtr-xml-utils

XSLT

firrtl-syntax

amba

FuseSoC-based reference SoC for the VeeR CPU family

VeeRwolf

Code-flow Integrity module to mitigate glitches and fault injections

EasyCLA-code_only

EasyCLA-specs_and_code

artwork

CHIPS Alliance artwork

caliptra-cfi

CHIPS Alliance Analog Working Group

rocket-pcblib

wg-analog

verible-actions-common

firtool-resolver

rocket-uncore