• Stars
    star
    147
  • Rank 242,259 (Top 5 %)
  • Language
    Scala
  • License
    Apache License 2.0
  • Created over 6 years ago
  • Updated 28 days ago

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Chisel/Firrtl execution engine

Treadle -- A Chisel/Firrtl Execution Engine


Join the chat at https://gitter.im/freechipsproject/firrtl Test

Treadle is an experimental circuit simulator that executes low Firrtl IR. It is based on earlier work on the firrtl_interpreter It will be one of the standard back-ends available as part of the chisel-testers project, and thus one of the tools in the freechipsproject/chisel3 hardware synthesis toolbox. This project provides a test harness supporting a peek, poke expect model.
It also provides a interactive simulator shell or repl (see treadle.sh) that allows fine grained incremental execution of a circuit. In combination with a scala debugger such as Eclipse or IntelliJ it can be a very powerful way of analyzing problematic behavior.

Chisel3 is a high-level functional circuit generator. It produces Flexible Intermediate Representation for RTL or FIRRTL. The Firrtl project parses and transforms firrtl. It also provides mechanisms for emitting verilog, for processing by downstream toolchains. Treadle parses and execute the LoFirrtl subset of Firrtl. Treadle has a short spin up time and is close to the performance of verilator simulations. It can be useful for an initial debugging of Chisel circuits and is also used for other forms of circuit analysis.

Using Treadle

Attach it to your project

If you are using the freechipsproject/chisel-testers you will have access to Treadle through it's dependency declarations.

If chisel-testers is not part of your tool chain then you must add the dependency explicitly. To do so, in your project build.sbt add a dependency on

"edu.berkeley.cs" %% "treadle" % "1.1-SNAPSHOT"

There are a number of different ways to specify this dependency in the build.sbt file. If you have based your circuit on the Chisel-template the addition should look like

libraryDependencies ++= Seq(
  "edu.berkeley.cs" %% "chisel3" % chiselVersion,
  "edu.berkeley.cs" %% "chisel-iotesters" % "1.0",
  "edu.berkeley.cs" %% "treadle" % "1.1-SNAPSHOT",
  "org.scalatest" %% "scalatest" % "3.2.8" % "test",
  "org.scalacheck" %% "scalacheck" % "1.12.4")

for other usage consult sbt documentation

Use the Tester Metaphor

The easiest way to invoke the interpreter is through a test based harness. The InterpretiveTester is very similar to the chisel ClassicTester, it's api consists of poke, peek and expect statements. Here is an example of a GCD Circuit

import chisel3._
import treadle.TreadleTester
import org.scalatest.{Matchers, FlatSpec}

object GCDCalculator {
  def computeGcd(a: Int, b: Int): (Int, Int) = {
    var x = a
    var y = b
    var depth = 1
    while(y > 0 ) {
      if (x > y) {
        x -= y
      }
      else {
        y -= x
      }
      depth += 1
    }
    (x, depth)
  }
}

class GCD extends Module {
  val io = IO(new Bundle {
    val a  = Input(UInt(16.W))
    val b  = Input(UInt(16.W)))
    val e  = Input(Bool())
    val z  = Output(UInt(16.W))
    val v  = Output(Bool())
  })
  val x  = Reg(UInt())
  val y  = Reg(UInt())
  when(x > y) { x := x - y }
    .elsewhen(x <= y) { y := y - x }
  when (io.e) { x := io.a; y := io.b }
  io.z := x
  io.v := y === UInt(0)
}

class TreadleUsageSpec extends FlatSpec with Matchers {

  "GCD" should "return correct values for a range of inputs" in {
    val s = Driver.emit(() => new GCD)

    val tester = TreadleTester(s)

    for {
      i <- 1 to 100
      j <- 1 to 100
    } {
      tester.poke("io_a", i)
      tester.poke("io_b", j)
      tester.poke("io_e", 1)
      tester.step()
      tester.poke("io_e", 0)

      var cycles = 0
      while (tester.peek("io_v") != BigInt(1)) {
        tester.step()
        cycles += 1
      }
      tester.expect("io_z", BigInt(GCDCalculator.computeGcd(i, j)._1))
      // uncomment the println to see a lot of output
      // println(f"GCD(${i}%3d, ${j}%3d) => ${interpretiveTester.peek("io_z")}%3d in $cycles%3d cycles")
    }
    tester.report()
  }
}

Style conventions ScalaFmt

Treadle is the first repo in the chisel family to use the ScalaFmt code formatter. The plan going forward from 12/9/2019 is that all Scala code in PRs to Treadle after that date must be formatted using the specification in the .scalafmt.conf file. Doing the formatting is simple and can be done via IntelliJ or sbt. More details can be found on the link above. For the present we are also interested in comments on the formatting decisions we have made. Keep in mind that there is no set of rules that will satisfy everyone.

About ports and names

The firrtl transformations that result in LoFirrtl alter the names of ports. What would be io.a becomes io_a and so forth.

More Repositories

1

chisel

Chisel: A Modern Hardware Design Language
Scala
3,691
star
2

rocket-chip

Rocket Chip Generator
Scala
2,986
star
3

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
C++
1,184
star
4

riscv-dv

Random instruction generator for RISC-V processor verification
Python
950
star
5

Cores-VeeR-EH1

VeeR EH1 core
SystemVerilog
771
star
6

firrtl

Flexible Intermediate Representation for RTL
Scala
690
star
7

chisel-template

A template project for beginning new Chisel work
Scala
517
star
8

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
C++
328
star
9

f4pga

FOSS Flow For FPGA
Python
310
star
10

f4pga-examples

Example designs showing different ways to use F4PGA toolchains.
Verilog
259
star
11

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
SystemVerilog
257
star
12

Cores-VeeR-EL2

VeeR EL2 Core
SystemVerilog
222
star
13

Cores-VeeR-EH2

SystemVerilog
202
star
14

dromajo

RISC-V RV64GC emulator designed for RTL co-simulation
C++
198
star
15

UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
C++
178
star
16

silicon-notebooks

Jupyter Notebook
143
star
17

synlig

SystemVerilog support for Yosys
Verilog
131
star
18

aib-phy-hardware

Advanced Interface Bus (AIB) die-to-die hardware open source
Verilog
117
star
19

VeeR-ISS

C++
103
star
20

fpga-tool-perf

FPGA tool performance profiling
Python
96
star
21

Caliptra

Caliptra IP and firmware for integrated Root of Trust block
94
star
22

fasm

FPGA Assembly (FASM) Parser and Generator
Python
85
star
23

yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.
Verilog
82
star
24

t1

Scala
81
star
25

omnixtend

OmniXtend cache coherence protocol
TeX
72
star
26

playground

chipyard in mill :P
Scala
72
star
27

uvm-verilator

SystemVerilog
52
star
28

caliptra-rtl

HW Design Collateral for Caliptra RoT IP
SystemVerilog
49
star
29

rocket-tools

Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
Shell
48
star
30

fpga-interchange-schema

Cap'n Proto
45
star
31

AIB-specification

Home of the Advanced Interface Bus (AIB) specification.
45
star
32

cde

A Scala library for Context-Dependent Environments
Scala
39
star
33

python-fpga-interchange

Python interface to FPGA interchange format
Python
39
star
34

Cores-SweRV_fpga

Tcl
38
star
35

firrtl-spec

The specification for the FIRRTL language
TeX
34
star
36

caliptra-sw

Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
Rust
31
star
37

espresso

C
31
star
38

UHDM-integration-tests

Verilog
29
star
39

f4pga-sdf-timing

Python library for working Standard Delay Format (SDF) Timing Annotation files.
Python
27
star
40

aib-phy-generator

AIB Generator: Analog hardware compiler for AIB PHY
Shell
26
star
41

verible-linter-action

Automatic SystemVerilog linting in github actions with the help of Verible
Python
25
star
42

riscv-fw-infrastructure

SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...
C
24
star
43

aib-protocols

SystemVerilog
20
star
44

systemc-compiler

Intel Compiler for SystemC
C++
18
star
45

tilelink

Scala
17
star
46

diplomacy

Scala
16
star
47

ideas

16
star
48

f4pga-xc7-bram-patch

Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.
LLVM
15
star
49

Cores-SweRV-Support-Package

Processor support packages
Python
15
star
50

rocket

The working draft to split rocket core out from rocket chip
Scala
14
star
51

homebrew-verible

Ruby
14
star
52

tools-cocotb-verilator-build

Makefile
14
star
53

rocket-chip-fpga-shells

Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
Scala
14
star
54

f4pga-bitstream-viewer

Tool for graphically viewing FPGA bitstream files and their connection to FASM features.
Python
13
star
55

caliptra-dpe

High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
Rust
13
star
56

OmnixtendEndpoint

Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.
Bluespec
12
star
57

rocket-chip-blocks

RTL blocks compatible with the Rocket Chip Generator
Scala
12
star
58

rocket-chip-inclusive-cache

An RTL generator for a last-level shared inclusive TileLink cache controller
Scala
11
star
59

foundation

Governance-related CHIPS Alliance documents, guides etc.
10
star
60

f4pga-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.
Python
10
star
61

f4pga-xc-fasm2bels

Library to convert a FASM file into BELs importable into Vivado.
Verilog
8
star
62

fpga-interchange-tests

Repository to run extensive tests on the FPGA interchange format
Verilog
8
star
63

tree-sitter-firrtl

FIRRTL grammar for tree-sitter
C++
8
star
64

verible-formatter-action

SystemVerilog
7
star
65

f4pga-database-visualizer

JavaScript
6
star
66

tsc

CHIPS Alliance Technical Steering Committee
5
star
67

f4pga-xc-fasm

Python
5
star
68

sv-tests-results

Output of the sv-tests runs.
HTML
4
star
69

caliptra-ureg

Rust
4
star
70

rocket-pcb

PCB libraries and templates for rocket-chip based FPGA/ASIC designs
Verilog
4
star
71

chips-alliance-website

SCSS
3
star
72

f4pga-rr-graph

Collection of Routing Resources Graph (RR Graph) libraries for VPR
Python
2
star
73

vtr-xml-utils

XSLT
2
star
74

VeeRwolf

FuseSoC-based reference SoC for the VeeR CPU family
Verilog
2
star
75

EasyCLA-code_only

1
star
76

EasyCLA-specs_and_code

1
star
77

artwork

CHIPS Alliance artwork
1
star
78

caliptra-cfi

Code-flow Integrity module to mitigate glitches and fault injections
Rust
1
star
79

rocket-pcblib

1
star
80

wg-analog

CHIPS Alliance Analog Working Group
1
star
81

firtool-resolver

Scala
1
star