Discover chipsalliance/rocket Open Source project

3,691

rocket-chip

Rocket Chip Generator

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

2,986

verible

Random instruction generator for RISC-V processor verification

1,184

riscv-dv

Cores-VeeR-EH1

firrtl

Flexible Intermediate Representation for RTL

A template project for beginning new Chisel work

690

chisel-template

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

517

Surelog

f4pga

f4pga-examples

Example designs showing different ways to use F4PGA toolchains.

Test suite designed to check compliance with the SystemVerilog standard.

259

sv-tests

Cores-VeeR-EL2

Cores-VeeR-EH2

dromajo

RISC-V RV64GC emulator designed for RTL co-simulation

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

198

UHDM

Chisel/Firrtl execution engine

178

treadle

silicon-notebooks

synlig

SystemVerilog support for Yosys

Advanced Interface Bus (AIB) die-to-die hardware open source

131

aib-phy-hardware

VeeR-ISS

fpga-tool-perf

FPGA tool performance profiling

Caliptra IP and firmware for integrated Root of Trust block

Caliptra

fasm

FPGA Assembly (FASM) Parser and Generator

Plugins for Yosys developed as part of the F4PGA project.

yosys-f4pga-plugins

OmniXtend cache coherence protocol

omnixtend

playground

uvm-verilator

caliptra-rtl

HW Design Collateral for Caliptra RoT IP

SystemVerilog

rocket-tools

Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)

Shell

fpga-interchange-schema

Cap'n Proto

AIB-specification

Home of the Advanced Interface Bus (AIB) specification.

cde

A Scala library for Context-Dependent Environments

Python interface to FPGA interchange format

python-fpga-interchange

The specification for the FIRRTL language

Cores-SweRV_fpga

Tcl

firrtl-spec

TeX

caliptra-sw

Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

espresso

UHDM-integration-tests

Python library for working Standard Delay Format (SDF) Timing Annotation files.

f4pga-sdf-timing

AIB Generator: Analog hardware compiler for AIB PHY

aib-phy-generator

Shell

verible-linter-action

Automatic SystemVerilog linting in github actions with the help of Verible

SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...

riscv-fw-infrastructure

aib-protocols

SystemVerilog

systemc-compiler

Intel Compiler for SystemC

tilelink

diplomacy

Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.

ideas

f4pga-xc7-bram-patch

LLVM

Cores-SweRV-Support-Package

Processor support packages

Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards

homebrew-verible

Ruby

tools-cocotb-verilator-build

Makefile

rocket-chip-fpga-shells

Tool for graphically viewing FPGA bitstream files and their connection to FASM features.

f4pga-bitstream-viewer

High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

caliptra-dpe

Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

OmnixtendEndpoint

Bluespec

rocket-chip-blocks

RTL blocks compatible with the Rocket Chip Generator

An RTL generator for a last-level shared inclusive TileLink cache controller

rocket-chip-inclusive-cache

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

foundation

f4pga-v2x

Library to convert a FASM file into BELs importable into Vivado.

f4pga-xc-fasm2bels

Repository to run extensive tests on the FPGA interchange format

fpga-interchange-tests

FIRRTL grammar for tree-sitter

tree-sitter-firrtl

CHIPS Alliance Technical Steering Committee

verible-formatter-action

SystemVerilog

f4pga-database-visualizer

JavaScript

tsc

f4pga-xc-fasm

Output of the sv-tests runs.

sv-tests-results

HTML

caliptra-ureg

PCB libraries and templates for rocket-chip based FPGA/ASIC designs

rocket-pcb

Collection of Routing Resources Graph (RR Graph) libraries for VPR

chips-alliance-website

SCSS

f4pga-rr-graph

FuseSoC-based reference SoC for the VeeR CPU family

vtr-xml-utils

XSLT

VeeRwolf

Code-flow Integrity module to mitigate glitches and fault injections

EasyCLA-code_only

EasyCLA-specs_and_code

artwork

CHIPS Alliance artwork

caliptra-cfi

CHIPS Alliance Analog Working Group

rocket-pcblib

wg-analog

firtool-resolver