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chisel
Chisel: A Modern Hardware Design Languagerocket-chip
Rocket Chip Generatorverible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language serverriscv-dv
Random instruction generator for RISC-V processor verificationCores-VeeR-EH1
VeeR EH1 corefirrtl
Flexible Intermediate Representation for RTLchisel-template
A template project for beginning new Chisel workSurelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsXf4pga
FOSS Flow For FPGAf4pga-examples
Example designs showing different ways to use F4PGA toolchains.sv-tests
Test suite designed to check compliance with the SystemVerilog standard.Cores-VeeR-EL2
VeeR EL2 CoreCores-VeeR-EH2
dromajo
RISC-V RV64GC emulator designed for RTL co-simulationUHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsXtreadle
Chisel/Firrtl execution enginesilicon-notebooks
synlig
SystemVerilog support for Yosysaib-phy-hardware
Advanced Interface Bus (AIB) die-to-die hardware open sourceVeeR-ISS
fpga-tool-perf
FPGA tool performance profilingCaliptra
Caliptra IP and firmware for integrated Root of Trust blockyosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.t1
omnixtend
OmniXtend cache coherence protocolplayground
chipyard in mill :Puvm-verilator
caliptra-rtl
HW Design Collateral for Caliptra RoT IProcket-tools
Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)fpga-interchange-schema
AIB-specification
Home of the Advanced Interface Bus (AIB) specification.cde
A Scala library for Context-Dependent Environmentspython-fpga-interchange
Python interface to FPGA interchange formatCores-SweRV_fpga
firrtl-spec
The specification for the FIRRTL languagecaliptra-sw
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and testespresso
UHDM-integration-tests
f4pga-sdf-timing
Python library for working Standard Delay Format (SDF) Timing Annotation files.aib-phy-generator
AIB Generator: Analog hardware compiler for AIB PHYverible-linter-action
Automatic SystemVerilog linting in github actions with the help of Veribleriscv-fw-infrastructure
SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...aib-protocols
systemc-compiler
Intel Compiler for SystemCtilelink
diplomacy
ideas
f4pga-xc7-bram-patch
Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.Cores-SweRV-Support-Package
Processor support packagesrocket
The working draft to split rocket core out from rocket chiphomebrew-verible
tools-cocotb-verilator-build
rocket-chip-fpga-shells
Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boardsf4pga-bitstream-viewer
Tool for graphically viewing FPGA bitstream files and their connection to FASM features.caliptra-dpe
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRsOmnixtendEndpoint
Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.rocket-chip-blocks
RTL blocks compatible with the Rocket Chip Generatorrocket-chip-inclusive-cache
An RTL generator for a last-level shared inclusive TileLink cache controllerfoundation
Governance-related CHIPS Alliance documents, guides etc.f4pga-v2x
Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.f4pga-xc-fasm2bels
Library to convert a FASM file into BELs importable into Vivado.fpga-interchange-tests
Repository to run extensive tests on the FPGA interchange formattree-sitter-firrtl
FIRRTL grammar for tree-sitterverible-formatter-action
f4pga-database-visualizer
tsc
CHIPS Alliance Technical Steering Committeef4pga-xc-fasm
sv-tests-results
Output of the sv-tests runs.caliptra-ureg
rocket-pcb
PCB libraries and templates for rocket-chip based FPGA/ASIC designschips-alliance-website
f4pga-rr-graph
Collection of Routing Resources Graph (RR Graph) libraries for VPRvtr-xml-utils
VeeRwolf
FuseSoC-based reference SoC for the VeeR CPU familyEasyCLA-code_only
EasyCLA-specs_and_code
artwork
CHIPS Alliance artworkcaliptra-cfi
Code-flow Integrity module to mitigate glitches and fault injectionsrocket-pcblib
wg-analog
CHIPS Alliance Analog Working Groupfirtool-resolver
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