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CHIPS Alliance (@chipsalliance)

chipsalliance

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Verilog 11.3 %

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8.8 %

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5.0 %

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2.5 %

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2.5 %

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2.5 %

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1.3 %

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1.3 %

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1.3 %

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1.3 %

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chisel

Chisel: A Modern Hardware Design Language

rocket-chip

Rocket Chip Generator

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Cores-VeeR-EH1

firrtl

Flexible Intermediate Representation for RTL

chisel-template

A template project for beginning new Chisel work

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

f4pga

FOSS Flow For FPGA

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2

f4pga-examples

Example designs showing different ways to use F4PGA toolchains.

Cores-VeeR-EL2

Cores-VeeR-EH2

dromajo

RISC-V RV64GC emulator designed for RTL co-simulation

UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Caliptra

Caliptra IP and firmware for integrated Root of Trust block

synlig

SystemVerilog support for Yosys

silicon-notebooks

Jupyter Notebook

treadle

Chisel/Firrtl execution engine

aib-phy-hardware

Advanced Interface Bus (AIB) die-to-die hardware open source

VeeR-ISS

t1

fpga-tool-perf

FPGA tool performance profiling

fasm

FPGA Assembly (FASM) Parser and Generator

caliptra-sw

Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

omnixtend

OmniXtend cache coherence protocol

playground

chipyard in mill :P

uvm-verilator

caliptra-rtl

HW Design Collateral for Caliptra RoT IP

riscv-vector-tests

Unit tests generator for RVV 1.0

fpga-interchange-schema

rocket-tools

Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)

AIB-specification

Home of the Advanced Interface Bus (AIB) specification.

firrtl-spec

The specification for the FIRRTL language

cde

A Scala library for Context-Dependent Environments

python-fpga-interchange

Python interface to FPGA interchange format

Cores-SweRV_fpga

espresso

UHDM-integration-tests

f4pga-sdf-timing

Python library for working Standard Delay Format (SDF) Timing Annotation files.

aib-phy-generator

AIB Generator: Analog hardware compiler for AIB PHY

verible-linter-action

Automatic SystemVerilog linting in github actions with the help of Verible

riscv-fw-infrastructure

SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...

systemc-compiler

Intel Compiler for SystemC

tilelink

aib-protocols

chisel-nix

Nix scripts used to manage the chisel projects.

ideas

f4pga-xc7-bram-patch

Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.

caliptra-dpe

High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

diplomacy

homebrew-verible

rocket-chip-inclusive-cache

An RTL generator for a last-level shared inclusive TileLink cache controller

rocket-chip-fpga-shells

Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards

chisel-interface

The 'missing header' for Chisel

rocket

The working draft to split rocket core out from rocket chip

OmnixtendEndpoint

Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

f4pga-bitstream-viewer

Tool for graphically viewing FPGA bitstream files and their connection to FASM features.

rocket-chip-blocks

RTL blocks compatible with the Rocket Chip Generator

Cores-SweRV-Support-Package

Processor support packages

tools-cocotb-verilator-build

f4pga-xc-fasm2bels

Library to convert a FASM file into BELs importable into Vivado.

foundation

Governance-related CHIPS Alliance documents, guides etc.

f4pga-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

tree-sitter-firrtl

FIRRTL grammar for tree-sitter

fpga-interchange-tests

Repository to run extensive tests on the FPGA interchange format

verible-formatter-action

f4pga-xc-fasm

rocket-pcb

PCB libraries and templates for rocket-chip based FPGA/ASIC designs

f4pga-database-visualizer

rocket-uncore

tac

CHIPS Alliance Technical Advisory Council

caliptra-ureg

sv-tests-results

Output of the sv-tests runs.

rvdecoderdb

The Scala parser to parse riscv/riscv-opcodes generate

chips-alliance-website

caliptra-ss

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

amba

i3c-core

f4pga-rr-graph

Collection of Routing Resources Graph (RR Graph) libraries for VPR

vtr-xml-utils

firrtl-syntax

TextMate-compatible description of FIRRTL syntax for use with GitHub's Linguist

EasyCLA-code_only

EasyCLA-specs_and_code

artwork

CHIPS Alliance artwork

caliptra-cfi

Code-flow Integrity module to mitigate glitches and fault injections

rocket-pcblib

wg-analog

CHIPS Alliance Analog Working Group

idealchisel

verible-actions-common

firtool-resolver