riscv/riscv-isa-manual

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RISC-V Instruction Set Manual

RISC-V Instruction Set Manual

This repository contains the source files for the RISC-V Instruction Set Manual, which is comprised of the Privileged RISC-V Instruction Set Manual (LaTeX) and the Unprivileged RISC-V Instruction Set Manual (AsciiDoc). The preface of each document indicates the version of each standard that has been formally ratified by RISC-V International.

This work is licensed under a Creative Commons Attribution 4.0 International License. See the LICENSE file for details.

The RISC-V Instruction Set Manual is organized into the following volumes:

Volume I: User-Level ISA
Volume II: Privileged Architecture

Official and Draft Versions

Official versions of the specifications are available at the RISC-V International website.
Compiled versions of the most recent drafts of the specifications can be found on the GitHub releases page.
Older official versions of the specifications are archived at the GitHub releases archive.

The canonical list of open-source RISC-V implementations' marchid CSR values is available in the marchid.md file.

Contributing

If you would like to contribute to this documentation, please refer to the Documentation Developer's Guide.

The recommended method for building the PDF files is to use the Docker Image, as described in the RISC-V Docs Base Container Image repository.

Alternative build methods, such as local builds and GitHub Action builds, are also available and described in the Documentation Developer's Guide.

riscv-v-spec

Working draft of the proposed RISC-V V vector extension

riscv-opcodes

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

sail-riscv

Sail RISC-V model

riscv-crypto

RISC-V cryptography extensions standardisation work.

meta-riscv

OpenEmbedded/Yocto layer for RISC-V Architecture

riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

learn

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

riscv-j-extension

Working Draft of the RISC-V J Extension Specification

riscv-p-spec

RISC-V Packed SIMD Extension

riscv-plic-spec

PLIC Specification

riscv-platform-specs

RISC-V Profiles and Platform Specification

riscv-profiles

RISC-V Architecture Profiles

riscv-cfi

This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.

docs-dev-guide

Documentation developer guide

riscv-aia

riscv-test-env

configuration-structure

RISC-V Configuration Structure

riscv-aclint

virtual-memory

riscv-bfloat16

riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

riscv-smmtt

This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.

docs-spec-template

riscv-smbios

RISC-V SMBIOS Type 44 Spec

docs-resources

riscv-spmp

The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.

riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

riscv-zacas

riscv-zacas created from docs-spec-template template

riscv-zabha

The Zabha extension provides support for byte and halfword atomic memory operations.

riscv-svadu

The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.

riscv-attached-matrix-facility

Attached Matrix Facility Specification

riscv-docs-base-container-image

A base container image populated with the dependencies to build the RISC-V Documentation.

riscv-b

"B" extension - that represents the collection of the Zba, Zbb, and Zbs extensions

riscv-zaamo-zalrsc

Zaamo / Zalrsc: A extension components

riscv-state-enable

riscv-smcntrpmf

Cycle & Instret Privilege Mode Filtering Architecture Extension

riscv-software-ecosystem

A curated list of the status of different softwares on RISC-V

riscv-double-trap

RISC-V Double Trap Fast-Track Extension

riscv-glossary

riscv-ssqosid

This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process.

riscv-indirect-csr-access

Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.

integrated-matrix-extension

Source code repository for the Integrated Matrix Facility Task Group

.github

riscv-ssrastraps

The RAS exception and interrupts extension (Ssrastraps) defines standard local interrupt numbers and exception-cause codes for reporting errors detected by RAS functions in the system.

riscv-zalasr

The ISA specification for the Zalasr extension.

riscv-performance-events

RISC-V Performance Events Specification

riscv-svvptc

Eliding Memory-management Fences on setting PTE valid (Svvptc)

riscv-pqc

Post Quantum Cryptography

riscv-ssdtso

The Ssdtso is a fast-track extension adding a 'dynamic-RVTSO' mode of operation and on-demand per-hart switching between the memory models.

lightweight-isolation

The Lightweight Isolation Specification

riscv-dot-product

Dot-Product Extension

riscv-hac

High Assurance Cryptography

riscv-smcdeleg-ssccfg

Supervisor Counter Delegation Architecture Extension

riscv-zilsd

Zilsd (Load/Store Pair for RV32) Fast-Track Extension

riscv-ras-eri

The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and configuring means to report the error to a handler component.