riscv/riscv-v-spec

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riscv/riscv-v-spec

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Working draft of the proposed RISC-V V vector extension

riscv-v-spec

Working draft of the proposed RISC-V V vector extension.

Version 1.0 has been frozen and at this time is undergoing public review. Version 1.0 is considered stable enough to begin developing toolchains, functional simulators, and implementations, including in upstream software projects, and is not expected to have incompatible changes except if serious issues are discovered during ratification. Once ratified, the spec will be given version 2.0.

The previous stable releases are v1.0-rc2, v1.0-rc1, v0.10, v0.9, and v0.8. Note, these previous releases were for experimental development purposes only and are not standard versions suitable for production use. Significant incompatible changes were made from these earlier versions prior to freezing.

The top level file is v-spec.adoc

Simply clicking on the file in the github repo viewer will render a usable version as markdown.

For a better rendering, use the documentation build process described below.

This work is licensed under a Creative Commons Attribution 4.0 International License. See the LICENSE file for details.

Additional Resources

The Spike simulator supports v1.0.
The RISC-V Proxy Kernel (to be used with e.g. Spike) supports v1.0 binaries.
The Binutils port for v0.8
The GNU toolchain port for v0.8
riscvOVPsim is a free RISC-V reference simulator that has support for v0.9, v0.8 and v0.7.1 (simulator is under a proprietary license, models are open source)

Documentation generator

Requirements

node v18.16.0+

Linux: install using nvm

macOS Homebrew: brew install node

macOS Macports: sudo port install npm6

Windows: nodejs.org

Install documentation generator

npm i

Build HTML/PDF documents

npm run build

Resulted files

public/*

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-opcodes

learn

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

sail-riscv

Sail RISC-V model

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

riscv-crypto

RISC-V cryptography extensions standardisation work.

meta-riscv

OpenEmbedded/Yocto layer for RISC-V Architecture

riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

riscv-j-extension

Working Draft of the RISC-V J Extension Specification

riscv-p-spec

RISC-V Packed SIMD Extension

riscv-plic-spec

PLIC Specification

riscv-profiles

RISC-V Architecture Profiles

riscv-cfi

This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.

docs-dev-guide

Documentation developer guide

riscv-CMOs

riscv-aia

riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

riscv-test-env

riscv-aclint

virtual-memory

configuration-structure

RISC-V Configuration Structure

riscv-smmtt

This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.

riscv-bfloat16

docs-resources

docs-spec-template

riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

riscv-smbios

RISC-V SMBIOS Type 44 Spec

riscv-double-trap

RISC-V Double Trap Fast-Track Extension

riscv-spmp

The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.

riscv-docs-base-container-image

A base container image populated with the dependencies to build the RISC-V Documentation.

riscv-zabha

The Zabha extension provides support for byte and halfword atomic memory operations.

riscv-attached-matrix-facility

Attached Matrix Facility Specification

riscv-glossary

riscv-zilsd

Zilsd (Load/Store Pair for RV32) Fast-Track Extension

riscv-software-ecosystem

A curated list of the status of different softwares on RISC-V

riscv-performance-events

RISC-V Performance Events Specification

riscv-b

"B" extension - that represents the collection of the Zba, Zbb, and Zbs extensions

riscv-zaamo-zalrsc

Zaamo / Zalrsc: A extension components

riscv-ssqosid

This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process.

.github

riscv-svvptc

Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)

riscv-memory-tagging

Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores

riscv-dot-product

Dot-Product Extension

riscv-smcdeleg-ssccfg

Supervisor Counter Delegation Architecture Extension

composable-custom-extensions

This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.

riscv-ssrastraps

The RAS exception and interrupts extension (Ssrastraps) defines standard local interrupt numbers and exception-cause codes for reporting errors detected by RAS functions in the system.

riscv-zalasr

The ISA specification for the Zalasr extension.

riscv-pqc

Post Quantum Cryptography

riscv-ssdtso

The Ssdtso is a fast-track extension adding a 'dynamic-RVTSO' mode of operation and on-demand per-hart switching between the memory models.

lightweight-isolation

The Lightweight Isolation Specification

riscv-hac

High Assurance Cryptography

riscv-ras-eri

The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and configuring means to report the error to a handler component.