riscv-isa-manual
RISC-V Instruction Set Manualriscv-v-spec
Working draft of the proposed RISC-V V vector extensionriscv-opcodes
RISC-V Opcodesriscv-debug-spec
Working Draft of the RISC-V Debug Specification Standardsail-riscv
Sail RISC-V modelriscv-crypto
RISC-V cryptography extensions standardisation work.meta-riscv
OpenEmbedded/Yocto layer for RISC-V Architectureriscv-fast-interrupt
Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)riscv-bitmanip
Working draft of the proposed RISC-V Bitmanipulation extensionlearn
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.riscv-j-extension
Working Draft of the RISC-V J Extension Specificationriscv-p-spec
RISC-V Packed SIMD Extensionriscv-plic-spec
PLIC Specificationriscv-platform-specs
RISC-V Profiles and Platform Specificationriscv-profiles
RISC-V Architecture Profilesriscv-cfi
This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.docs-dev-guide
Documentation developer guideriscv-aia
riscv-test-env
configuration-structure
RISC-V Configuration Structureriscv-aclint
virtual-memory
riscv-bfloat16
riscv-cheri
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.riscv-smmtt
This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.docs-spec-template
riscv-smbios
RISC-V SMBIOS Type 44 Specdocs-resources
riscv-spmp
The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.riscv-control-transfer-records
This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.riscv-zacas
riscv-zacas created from docs-spec-template templateriscv-zabha
The Zabha extension provides support for byte and halfword atomic memory operations.riscv-svadu
The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.riscv-attached-matrix-facility
Attached Matrix Facility Specificationriscv-docs-base-container-image
A base container image populated with the dependencies to build the RISC-V Documentation.riscv-b
"B" extension - that represents the collection of the Zba, Zbb, and Zbs extensionsriscv-zaamo-zalrsc
Zaamo / Zalrsc: A extension componentsriscv-state-enable
riscv-smcntrpmf
Cycle & Instret Privilege Mode Filtering Architecture Extensionriscv-software-ecosystem
A curated list of the status of different softwares on RISC-Vriscv-double-trap
RISC-V Double Trap Fast-Track Extensionriscv-glossary
riscv-ssqosid
This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process.riscv-indirect-csr-access
Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.integrated-matrix-extension
Source code repository for the Integrated Matrix Facility Task Group.github
riscv-ssrastraps
The RAS exception and interrupts extension (Ssrastraps) defines standard local interrupt numbers and exception-cause codes for reporting errors detected by RAS functions in the system.riscv-zalasr
The ISA specification for the Zalasr extension.riscv-performance-events
RISC-V Performance Events Specificationriscv-svvptc
Eliding Memory-management Fences on setting PTE valid (Svvptc)riscv-pqc
Post Quantum Cryptographyriscv-ssdtso
The Ssdtso is a fast-track extension adding a 'dynamic-RVTSO' mode of operation and on-demand per-hart switching between the memory models.lightweight-isolation
The Lightweight Isolation Specificationriscv-dot-product
Dot-Product Extensionriscv-hac
High Assurance Cryptographyriscv-smcdeleg-ssccfg
Supervisor Counter Delegation Architecture Extensionriscv-zilsd
Zilsd (Load/Store Pair for RV32) Fast-Track Extensionriscv-ras-eri
The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and configuring means to report the error to a handler component.Love Open Source and this site? Check out how you can help us