• Stars
    star
    2
  • Language Makefile
  • License
    Creative Commons ...
  • Created 7 months ago
  • Updated 7 months ago

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores

More Repositories

1

riscv-isa-manual

RISC-V Instruction Set Manual
TeX
3,546
star
2

riscv-v-spec

Working draft of the proposed RISC-V V vector extension
Assembly
961
star
3

riscv-opcodes

RISC-V Opcodes
Python
657
star
4

learn

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
462
star
5

sail-riscv

Sail RISC-V model
Coq
455
star
6

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard
Python
454
star
7

riscv-crypto

RISC-V cryptography extensions standardisation work.
C
358
star
8

meta-riscv

OpenEmbedded/Yocto layer for RISC-V Architecture
BitBake
350
star
9

riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
Makefile
236
star
10

riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension
Makefile
205
star
11

riscv-j-extension

Working Draft of the RISC-V J Extension Specification
Makefile
160
star
12

riscv-p-spec

RISC-V Packed SIMD Extension
138
star
13

riscv-plic-spec

PLIC Specification
125
star
14

riscv-profiles

RISC-V Architecture Profiles
Makefile
104
star
15

riscv-cfi

This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.
Makefile
83
star
16

docs-dev-guide

Documentation developer guide
TeX
79
star
17

riscv-CMOs

HTML
77
star
18

riscv-aia

77
star
19

riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
Python
50
star
20

riscv-test-env

C
40
star
21

riscv-aclint

Makefile
39
star
22

virtual-memory

35
star
23

configuration-structure

RISC-V Configuration Structure
Python
35
star
24

riscv-smmtt

This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
Makefile
26
star
25

riscv-bfloat16

Makefile
26
star
26

docs-resources

19
star
27

docs-spec-template

Makefile
18
star
28

riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
Makefile
14
star
29

riscv-smbios

RISC-V SMBIOS Type 44 Spec
TeX
13
star
30

riscv-double-trap

RISC-V Double Trap Fast-Track Extension
Makefile
12
star
31

riscv-spmp

The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.
TeX
11
star
32

riscv-docs-base-container-image

A base container image populated with the dependencies to build the RISC-V Documentation.
9
star
33

riscv-zabha

The Zabha extension provides support for byte and halfword atomic memory operations.
Makefile
8
star
34

riscv-attached-matrix-facility

Attached Matrix Facility Specification
Makefile
6
star
35

riscv-glossary

Makefile
6
star
36

riscv-zilsd

Zilsd (Load/Store Pair for RV32) Fast-Track Extension
Makefile
6
star
37

riscv-software-ecosystem

A curated list of the status of different softwares on RISC-V
5
star
38

riscv-performance-events

RISC-V Performance Events Specification
Makefile
4
star
39

riscv-b

"B" extension - that represents the collection of the Zba, Zbb, and Zbs extensions
Makefile
4
star
40

riscv-zaamo-zalrsc

Zaamo / Zalrsc: A extension components
Makefile
4
star
41

riscv-ssqosid

This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process.
Makefile
2
star
42

.github

2
star
43

riscv-svvptc

Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)
Makefile
2
star
44

riscv-dot-product

Dot-Product Extension
Makefile
2
star
45

riscv-smcdeleg-ssccfg

Supervisor Counter Delegation Architecture Extension
Makefile
2
star
46

composable-custom-extensions

This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.
Makefile
1
star
47

riscv-ssrastraps

The RAS exception and interrupts extension (Ssrastraps) defines standard local interrupt numbers and exception-cause codes for reporting errors detected by RAS functions in the system.
TeX
1
star
48

riscv-zalasr

The ISA specification for the Zalasr extension.
Makefile
1
star
49

riscv-pqc

Post Quantum Cryptography
Makefile
1
star
50

riscv-ssdtso

The Ssdtso is a fast-track extension adding a 'dynamic-RVTSO' mode of operation and on-demand per-hart switching between the memory models.
Makefile
1
star
51

lightweight-isolation

The Lightweight Isolation Specification
Makefile
1
star
52

riscv-hac

High Assurance Cryptography
Makefile
1
star
53

riscv-ras-eri

The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and configuring means to report the error to a handler component.
TeX
1
star