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riscv-isa-manual
RISC-V Instruction Set Manualriscv-v-spec
Working draft of the proposed RISC-V V vector extensionriscv-opcodes
RISC-V Opcodeslearn
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.sail-riscv
Sail RISC-V modelriscv-debug-spec
Working Draft of the RISC-V Debug Specification Standardriscv-crypto
RISC-V cryptography extensions standardisation work.meta-riscv
OpenEmbedded/Yocto layer for RISC-V Architectureriscv-fast-interrupt
Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)riscv-bitmanip
Working draft of the proposed RISC-V Bitmanipulation extensionriscv-j-extension
Working Draft of the RISC-V J Extension Specificationriscv-p-spec
RISC-V Packed SIMD Extensionriscv-plic-spec
PLIC Specificationriscv-profiles
RISC-V Architecture Profilesriscv-cfi
This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.riscv-CMOs
riscv-aia
riscv-cheri
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.riscv-test-env
riscv-aclint
virtual-memory
configuration-structure
RISC-V Configuration Structureriscv-smmtt
This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.riscv-bfloat16
docs-resources
docs-spec-template
riscv-control-transfer-records
This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.riscv-smbios
RISC-V SMBIOS Type 44 Specriscv-double-trap
RISC-V Double Trap Fast-Track Extensionriscv-spmp
The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.riscv-docs-base-container-image
A base container image populated with the dependencies to build the RISC-V Documentation.riscv-zabha
The Zabha extension provides support for byte and halfword atomic memory operations.riscv-attached-matrix-facility
Attached Matrix Facility Specificationriscv-glossary
riscv-zilsd
Zilsd (Load/Store Pair for RV32) Fast-Track Extensionriscv-software-ecosystem
A curated list of the status of different softwares on RISC-Vriscv-performance-events
RISC-V Performance Events Specificationriscv-b
"B" extension - that represents the collection of the Zba, Zbb, and Zbs extensionsriscv-zaamo-zalrsc
Zaamo / Zalrsc: A extension componentsriscv-ssqosid
This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process..github
riscv-svvptc
Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)riscv-memory-tagging
Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and storesriscv-dot-product
Dot-Product Extensionriscv-smcdeleg-ssccfg
Supervisor Counter Delegation Architecture Extensioncomposable-custom-extensions
This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.riscv-ssrastraps
The RAS exception and interrupts extension (Ssrastraps) defines standard local interrupt numbers and exception-cause codes for reporting errors detected by RAS functions in the system.riscv-zalasr
The ISA specification for the Zalasr extension.riscv-pqc
Post Quantum Cryptographyriscv-ssdtso
The Ssdtso is a fast-track extension adding a 'dynamic-RVTSO' mode of operation and on-demand per-hart switching between the memory models.lightweight-isolation
The Lightweight Isolation Specificationriscv-hac
High Assurance Cryptographyriscv-ras-eri
The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and configuring means to report the error to a handler component.Love Open Source and this site? Check out how you can help us