• Stars
    star
    162
  • Rank 232,284 (Top 5 %)
  • Language
    C++
  • License
    GNU General Publi...
  • Created over 9 years ago
  • Updated almost 3 years ago

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Open source implementation of a Verilog formatter

iStyle v1

Fast and Free Automatic Formatter for Verilog Source Code

    Created by haimag
    Thanks to Tal Davidson & Astyle
    Report bugs https://github.com/thomasrussellmurphy/istyle-verilog-formatter/issues

Originally hosted at http://code.google.com/p/istyle-verilog-formatter before Google Code EOL

Usage:
    iStyle [options] Foo.v  B*r.v  [...]
    OR, use stdin/stdout
    iStyle [options] <Foo.v >Foo_formatted.v

When indenting a specific file, the resulting indented file RETAINS the
original file-name. The original pre-indented file is renamed, with a
suffix of ".orig" added to the original filename.

By default, iStyle is set up to indent Verilog files, with 4 spaces per
indent, a maximal indentation of 40 spaces inside continuous statements,
and NO formatting.

Option's Format:


    Long options (starting with '--') must be written one at a time.
    Short options (starting with '-') may be appended together.
    Thus, -bps4 is the same as -b -p -s4.

Predefined Styling options:


    --style=ansi
    ANSI style formatting/indenting.

    --style=kr
    Kernighan&Ritchie style formatting/indenting.

    --style=gnu
    GNU style formatting/indenting.

Indentation options:


    -s   OR   -s#   OR   --indent=spaces=#
    Indent using # spaces per indent. Not specifying #
    will result in a default of 4 spaces per indent.

    -t   OR   -t#   OR   --indent=tab=#
    Indent using tab characters, assuming that each
    tab is # spaces long. Not specifying # will result
    in a default assumption of 4 spaces per tab.

    -T#   OR   --force-indent=tab=#
    Indent using tab characters, assuming that each
    tab is # spaces long. Force tabs to be used in areas
    iStyle would prefer to use spaces.

    -B   OR   --indent-brackets
    Add extra indentation to 'begin' and 'end' block brackets.

    -G   OR   --indent-blocks
    Add extra indentation entire blocks (including brackets).

    -m#  OR  --min-conditional-indent=#
    Indent a minimal # spaces in a continuous conditional
    belonging to a conditional header.

    -M#  OR  --max-instatement-indent=#
    Indent a maximal # spaces in a continuous statement,
    relatively to the previous line.

    -E  OR  --fill-empty-lines
    Fill empty lines with the white space of their
    previous lines.

    --indent-preprocessor
    Indent multi-line #define statements

Formatting options:


    -b  OR  --brackets=break
    Break brackets from pre-block code (i.e. ANSI C/C++ style).

    -a  OR  --brackets=attach
    Attach brackets to pre-block code (i.e. Java/K&R style).

    -o   OR  --one-line=keep-statements
    Don't break lines containing multiple statements into
    multiple single-statement lines.

    -O   OR  --one-line=keep-blocks
    Don't break blocks residing completely on one line

    -p   OR  --pad=oper
    Insert space paddings around operators only.

    --pad=paren
    Insert space paddings around parenthesies only.
    -l OR --pad=block
    Enclose one statement in a begin-end only for keyword if/else/while/for.

    -P   OR  --pad=all
    Insert space paddings around operators AND parenthesies.

    --convert-tabs
    Convert tabs to spaces.

    --break-blocks
    Insert empty lines around unrelated blocks, labels, ...

    --break-blocks=all
    Like --break-blocks, except also insert empty lines
    around closing headers (e.g. 'else', ...).

    --break-elseifs
    Break 'else if()' statements into two different lines.

Other options:


    --suffix=####
    Append the suffix #### instead of '.orig' to original filename.

    -n   OR  --suffix=none
    Tells Astyle not to keep backups of the original source files.
    WARNING: Use this option with care, as Astyle comes with NO WARRANTY...

    -X   OR  --errors-to-standard-output
    Print errors and help information to standard-output rather than
    to standard-error.

    -v   OR   --version
    Print version number

    -h   OR   -?   OR   --help
    Print this help message

    --options=####  OR --options=none
    Parse used the specified options file: ####, options=none, none
    parse options file, and not looks for parse options files

Default options file:


    iStyle looks for a default options file in the following order:
    1. The contents of the ISTYLE_OPTIONS environment
       variable if it exists.
    2. The file called .iStylerc in the directory pointed to by the
       HOME environment variable ( i.e. $HOME/.iStylerc ).
    3. The file called .iStylerc in the directory pointed to by the
       HOMEPATH environment variable ( i.e. %HOMEPATH%\.iStylerc ).
    If a default options file is found, the options in this file
    will be parsed BEFORE the command-line options.
    Options within the default option file may be written without
    the preliminary '-' or '--'.

More Repositories

1

stx_cookbook

Altera Advanced Synthesis Cookbook 11.0
Verilog
66
star
2

MARS_Assembler

A one-time mirror for "MARS" source code for an undergrad project.
Java
17
star
3

quartus-DE1_SOC-project

A default project for Terasic's DE1_SOC Altera Cyclone V SoC Development Boards
Python
10
star
4

quartus-DE0-project

Default project plus project creator for Terasic's DE0 Altera Cyclone III Development Boards
Verilog
5
star
5

adb_converter

A subset of tmk/tmk_keyboard with just the Apple Desktop Bus functionality.
C
4
star
6

xilinx_xstug_examples

Unzipped for ease of access: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip
VHDL
4
star
7

LaTeX-Templates

Templates for LaTeX that I have accumulated or written over time.
TeX
3
star
8

CWRU-THESIS-TEX-MODE

From the depths of the Case network, I found. . .
TeX
3
star
9

adb-to-usb

Manufacturing information for my Apple Desktop Bus to USB keyboard converters.
3
star
10

altera_fir_variable_saturation

An implementation of a 4-bank gain select for reducing a 35-bit signed Avalon ST data stream to a 12-bit signed Avalon ST data stream using a combination of MSB saturation and LSB truncation. For CWRU EECS 301 Lab 4: Spring 2015, Fall 2015.
VHDL
2
star
11

CVGX_1024_00_M1CDCE

Quartus project for 1024-00 testing stage M1: CDCE
Verilog
2
star
12

ise-basys2-project

Default project for Digilent's Basys2 Xilinx Spartan-3e Development Boards
VHDL
2
star
13

eecs318-fall2015

My work for CWRU EECS 318 Fall 2015
VHDL
2
star
14

CVGX_1024_01_M4

Integration of components, code, and knowledge to bring up the 1024-01
Verilog
1
star
15

EECS_301_Labs

EECS 301 Spring 2014 Projects: Thomas Murphy and Camille Jackman
VHDL
1
star
16

basys2_demo_git_test

Messing with getting Git and Xilinx ISE working together-ish.
VHDL
1
star
17

CVGX_starter_kit_templates

Generated Terasic Cyclone V GX Starter Kit projects from the System Builder for my reference
Verilog
1
star
18

basys2-display

Trying to operate a F-51933GNF-SLW-ACN-ND
VHDL
1
star
19

basys2-spi

VHDL
1
star
20

1024_fpga_preparations

Preparing information and material for bringup of 1024 designs
Python
1
star
21

de0_state_machine

Working with VHDL to make a state machine on the DE0
VHDL
1
star
22

thomasrussellmurphy.github.io

How about a personal site through github.io?
CSS
1
star
23

basys2-blinky-lights

Getting something concrete done with the Basys2 by blinking lights
VHDL
1
star
24

CVGX_1024_00_M1AFE

Quartus project for 1024-00 testing stage M1: AFE
Verilog
1
star
25

de1_soc_example

A short example for using the DE1_SOC Terasic development board
Verilog
1
star
26

basys2-lfsr

Using a LFSR to control LEDs because why not.
VHDL
1
star
27

CVGX_GPIO_HSMC_LVDS

Verilog
1
star
28

lcd_video_demonstration_skeleton_de1

A simple screen demonstration for CWRU EECS 301 expansion board LCD video, requiring implementing the screen controller. Now for the DE1-SoC.
Verilog
1
star
29

lcd_video_demonstration_skeleton

A simple screen demonstration for CWRU EECS 301 expansion board LCD video, requiring implementing the screen controller
Verilog
1
star
30

eecs_301_reference_designs_2015_spring

Reference designs for CWRU EECS 301 labs assigned Spring 2015
Verilog
1
star