Discover thomasrussellmurphy/lcd_video_demonstration

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Created over 9 years ago
Updated over 9 years ago

thomasrussellmurphy

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A simple screen demonstration for CWRU EECS 301 expansion board LCD video, requiring implementing the screen controller

istyle-verilog-formatter

Open source implementation of a Verilog formatter

C++

162

stx_cookbook

Altera Advanced Synthesis Cookbook 11.0

Verilog

MARS_Assembler

A one-time mirror for "MARS" source code for an undergrad project.

Java

quartus-DE1_SOC-project

A default project for Terasic's DE1_SOC Altera Cyclone V SoC Development Boards

Python

quartus-DE0-project

Default project plus project creator for Terasic's DE0 Altera Cyclone III Development Boards

Verilog

adb_converter

A subset of tmk/tmk_keyboard with just the Apple Desktop Bus functionality.

xilinx_xstug_examples

Unzipped for ease of access: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip

VHDL

LaTeX-Templates

Templates for LaTeX that I have accumulated or written over time.

TeX

CWRU-THESIS-TEX-MODE

From the depths of the Case network, I found. . .

TeX

adb-to-usb

Manufacturing information for my Apple Desktop Bus to USB keyboard converters.

altera_fir_variable_saturation

An implementation of a 4-bank gain select for reducing a 35-bit signed Avalon ST data stream to a 12-bit signed Avalon ST data stream using a combination of MSB saturation and LSB truncation. For CWRU EECS 301 Lab 4: Spring 2015, Fall 2015.

VHDL

CVGX_1024_00_M1CDCE

Quartus project for 1024-00 testing stage M1: CDCE

Verilog

ise-basys2-project

Default project for Digilent's Basys2 Xilinx Spartan-3e Development Boards

VHDL

eecs318-fall2015

My work for CWRU EECS 318 Fall 2015

VHDL

CVGX_1024_01_M4

Integration of components, code, and knowledge to bring up the 1024-01

Verilog

EECS_301_Labs

EECS 301 Spring 2014 Projects: Thomas Murphy and Camille Jackman

VHDL

basys2_demo_git_test

Messing with getting Git and Xilinx ISE working together-ish.

VHDL

CVGX_starter_kit_templates

Generated Terasic Cyclone V GX Starter Kit projects from the System Builder for my reference

Verilog

basys2-display

Trying to operate a F-51933GNF-SLW-ACN-ND

VHDL

basys2-spi

VHDL

1024_fpga_preparations

Preparing information and material for bringup of 1024 designs

Python

de0_state_machine

Working with VHDL to make a state machine on the DE0

VHDL

thomasrussellmurphy.github.io

How about a personal site through github.io?

CSS

basys2-blinky-lights

Getting something concrete done with the Basys2 by blinking lights

VHDL

CVGX_1024_00_M1AFE

Quartus project for 1024-00 testing stage M1: AFE

Verilog

de1_soc_example

A short example for using the DE1_SOC Terasic development board

Verilog

basys2-lfsr

Using a LFSR to control LEDs because why not.

VHDL

CVGX_GPIO_HSMC_LVDS

Verilog

lcd_video_demonstration_skeleton_de1

A simple screen demonstration for CWRU EECS 301 expansion board LCD video, requiring implementing the screen controller. Now for the DE1-SoC.

Verilog

eecs_301_reference_designs_2015_spring

Reference designs for CWRU EECS 301 labs assigned Spring 2015

Verilog

thomasrussellmurphy/lcd_video_demonstration_skeleton

thomasrussellmurphy

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