Thomas Russell Murphy (@thomasrussellmurphy)
github

thomasrussellmurphy

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  • Stars
    star
    292
  • Global Rank 91,044 (Top 4 %)
  • Followers 39
  • Following 40
  • Registered about 12 years ago
  • Most used languages
    Verilog     36.7 %
    VHDL     36.7 %
    TeX
         6.7 %
    Python
         6.7 %
    C++
         3.3 %
    CSS
         3.3 %
    C
         3.3 %
    Java
         3.3 %
  • Location πŸ‡ΊπŸ‡Έ United States
  • Country Total Rank 21,761
  • Country Ranking
    Verilog     68
    VHDL     79
    TeX
         1,748
    C++
         1,791
    Java
         7,679

Top repositories

1

istyle-verilog-formatter

Open source implementation of a Verilog formatter
C++
162
star
2

stx_cookbook

Altera Advanced Synthesis Cookbook 11.0
Verilog
66
star
3

MARS_Assembler

A one-time mirror for "MARS" source code for an undergrad project.
Java
17
star
4

quartus-DE1_SOC-project

A default project for Terasic's DE1_SOC Altera Cyclone V SoC Development Boards
Python
10
star
5

quartus-DE0-project

Default project plus project creator for Terasic's DE0 Altera Cyclone III Development Boards
Verilog
5
star
6

adb_converter

A subset of tmk/tmk_keyboard with just the Apple Desktop Bus functionality.
C
4
star
7

xilinx_xstug_examples

Unzipped for ease of access: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip
VHDL
4
star
8

LaTeX-Templates

Templates for LaTeX that I have accumulated or written over time.
TeX
3
star
9

CWRU-THESIS-TEX-MODE

From the depths of the Case network, I found. . .
TeX
3
star
10

adb-to-usb

Manufacturing information for my Apple Desktop Bus to USB keyboard converters.
3
star
11

altera_fir_variable_saturation

An implementation of a 4-bank gain select for reducing a 35-bit signed Avalon ST data stream to a 12-bit signed Avalon ST data stream using a combination of MSB saturation and LSB truncation. For CWRU EECS 301 Lab 4: Spring 2015, Fall 2015.
VHDL
2
star
12

CVGX_1024_00_M1CDCE

Quartus project for 1024-00 testing stage M1: CDCE
Verilog
2
star
13

ise-basys2-project

Default project for Digilent's Basys2 Xilinx Spartan-3e Development Boards
VHDL
2
star
14

eecs318-fall2015

My work for CWRU EECS 318 Fall 2015
VHDL
2
star
15

CVGX_1024_01_M4

Integration of components, code, and knowledge to bring up the 1024-01
Verilog
1
star
16

EECS_301_Labs

EECS 301 Spring 2014 Projects: Thomas Murphy and Camille Jackman
VHDL
1
star
17

basys2_demo_git_test

Messing with getting Git and Xilinx ISE working together-ish.
VHDL
1
star
18

CVGX_starter_kit_templates

Generated Terasic Cyclone V GX Starter Kit projects from the System Builder for my reference
Verilog
1
star
19

basys2-display

Trying to operate a F-51933GNF-SLW-ACN-ND
VHDL
1
star
20

basys2-spi

VHDL
1
star
21

1024_fpga_preparations

Preparing information and material for bringup of 1024 designs
Python
1
star
22

de0_state_machine

Working with VHDL to make a state machine on the DE0
VHDL
1
star
23

thomasrussellmurphy.github.io

How about a personal site through github.io?
CSS
1
star
24

basys2-blinky-lights

Getting something concrete done with the Basys2 by blinking lights
VHDL
1
star
25

CVGX_1024_00_M1AFE

Quartus project for 1024-00 testing stage M1: AFE
Verilog
1
star
26

de1_soc_example

A short example for using the DE1_SOC Terasic development board
Verilog
1
star
27

basys2-lfsr

Using a LFSR to control LEDs because why not.
VHDL
1
star
28

CVGX_GPIO_HSMC_LVDS

Verilog
1
star
29

lcd_video_demonstration_skeleton_de1

A simple screen demonstration for CWRU EECS 301 expansion board LCD video, requiring implementing the screen controller. Now for the DE1-SoC.
Verilog
1
star
30

lcd_video_demonstration_skeleton

A simple screen demonstration for CWRU EECS 301 expansion board LCD video, requiring implementing the screen controller
Verilog
1
star
31

eecs_301_reference_designs_2015_spring

Reference designs for CWRU EECS 301 labs assigned Spring 2015
Verilog
1
star