riscvarchive/risc-v-getting-started-guide

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The official RISC-V getting started guide

RISC-V Getting Started Guide

This is the repository for the RISC-V Getting Started Guide, an introductory material prepared by the RISC-V Foundation and hosted at Read The Docs to show you where to start if you're interested in developing for the free and open source ISA.

For details about RISC-V itself, see the RISC-V Website.

You can contribute to the Getting Started Guide too! We are always happy to add more platforms and examples, and make the Guide more attractive to readers. See Contributing below for details.

Compiling the Guide

The Guide is built using Sphinx, a popular documentation framework used e.g. by Python, Zephyr and Linux, based on reStructuredText.

Sphinx can be installed with pip, the Python package manager:

pip install sphinx

(for detailed instructions, see Installing Sphinx)

To compile the HTML version of the Guide, use:

make html

The output will reside in the build/ directory.

You can also generate a PDF, which requires TeX and a few other tools.

Contributing

The RISC-V ecosystem is largely based around a diversified pool of corporate and personal contributions coming from over 130 corporate members and thousands of developers around the world. We especially welcome contributions that make RISC-V more accessible to the broader public (such as improving this Guide) - and we are happy you are reading this!

Please use the GitHub issues and pull requests mechanisms to contribute to the Guide. This may include:

guides for new platforms (please follow the style in which existing platforms are written)
corrections and extensions to existing platforms
more advanced pieces of content showcasing additional software that can be run on RISC-V

Note that in order to keep the material universally accessible, please only contribute guides based on software that is freely available without unnecessary limitation.

New platform contributions should be complete and tested on multiple platforms (or at least explicitly marked as incomplete in some aspects), so that users can get started successfully without running into problems.

For the sake of clarity, legibility and user-friendliness, the RISC-V Foundation reserves the right to modify or refuse to include submitted pieces of content at its discretion.

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-linux

RISC-V Linux Port

riscv-software-list

The RISC-V software tools list, as seen on riscv.org

riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support

riscv-gcc

riscv-wiki

educational-materials

Educational materials for RISC-V

riscv-go

riscv-code-size-reduction

riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.

riscv-platform-specs

RISC-V Profiles and Platform Specification

riscv-newlib

RISC-V port of newlib

riscv-musl

musl libc for RISC-V

ISA_Formal_Spec_Public_Review

Locus site for Public Review of Several RISC-V ISA Formal Specs

riscv-glibc

RISC-V port of GNU's libc

riscv-fesvr

RISC-V Frontend Server

riscv-poky

Port of the Yocto Project to the RISC-V ISA

riscv-tee

riscv-clang

riscv-eabi-spec

Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.

riscv-lld

RISC-V port of LLVM Linker

riscv-edk2

Port of EDK2 implementation of UEFI to RISC-V. See documentation at:

riscv-gentoo

A port of Gentoo to RISC-V

riscv-zicond

The ISA specification for the ZiCondOps extension.

riscv-old-gcc

gcc+newlib and gcc+glibc toolchains

riscv-edk2-platforms

Port of EDK2 implementation of UEFI to RISC-V. See documentation at:

riscv-4th-workshop-tutorials

4th RISC-V Workshop Tutorials

riscv-zfinx

riscv-strace

RISC-V strace port

riscv-dejagnu

DejaGnu RISC-V port

documents

riscv.github.io

riscv-gentoo-infra

Infrastructure for building Gentoo for RISC-V

riscv-buildroot

RISC-V Buildroot

riscv-alt-fp

RISC-V Alternate FP Format

riscv-zacas

riscv-zacas created from docs-spec-template template

debug-taskgroup

Overview page for the RISC-V debug task group

riscv-weekly

RISC-V Weekly Community Update

riscv-libffi

RISC-V libffi port

riscv-buildbot-infra

The RISC-V buildbot infastructure

riscv-watchdog

riscv-crossdev

A RISC-V Port of Gentoo's Crossdev

riscv-svadu

The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.

riscv-zawrs

The repo will be used to hold the draft Zawrs (fast-track) extension and to make releases for reviews.

groups

RISC-V Technical Working Groups - charter, meeting minutes, planning documents

genz-on-riscv

riscv-sail-archive

riscv-time-compare

blockchain

Blockchain SIG Community

riscv-linux-infra

Scripts to help manager the RISC-V Linux codebase

riscv-state-enable

riscv-smcntrpmf

Cycle & Instret Privilege Mode Filtering Architecture Extension

riscv-indirect-csr-access

Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.

riscv-unix-class-platform-spec

RISC-V UNIX-class Platform Specification

riscv-count-overflow

mem-model

Private repo for the Memory Model Task Group

unified-discovery

automotive

Group administration repository for SIG: Automotive

riscv-CMOs-discuss

riscv-ras-terms-defs

The RAS Terms & Definitions specification define the terms and definitions for physical mechanisms starting from common ones from research and development to adapting the terms as needed.