riscvarchive/riscv-gcc

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riscvarchive/riscv-gcc

riscvarchive

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This directory contains the GNU Compiler Collection (GCC).

The GNU Compiler Collection is free software.  See the files whose
names start with COPYING for copying permission.  The manuals, and
some of the runtime libraries, are under different terms; see the
individual source files for details.

The directory INSTALL contains copies of the installation information
as HTML and plain text.  The source of this information is
gcc/doc/install.texi.  The installation information includes details
of what is included in the GCC sources and what files GCC installs.

See the file gcc/doc/gcc.texi (together with other files that it
includes) for usage and porting information.  An online readable
version of the manual is in the files gcc/doc/gcc.info*.

See http://gcc.gnu.org/bugs/ for how to report bugs usefully.

Copyright years on GCC source files may be listed using range
notation, e.g., 1987-2012, indicating that every year in the range,
inclusive, is a copyrightable year that could otherwise be listed
individually.

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-linux

RISC-V Linux Port

riscv-software-list

The RISC-V software tools list, as seen on riscv.org

riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support

riscv-wiki

educational-materials

Educational materials for RISC-V

risc-v-getting-started-guide

The official RISC-V getting started guide

riscv-go

riscv-code-size-reduction

riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.

riscv-platform-specs

RISC-V Profiles and Platform Specification

riscv-newlib

RISC-V port of newlib

riscv-musl

musl libc for RISC-V

ISA_Formal_Spec_Public_Review

Locus site for Public Review of Several RISC-V ISA Formal Specs

riscv-glibc

RISC-V port of GNU's libc

riscv-fesvr

RISC-V Frontend Server

riscv-poky

Port of the Yocto Project to the RISC-V ISA

riscv-tee

riscv-clang

riscv-eabi-spec

Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.

riscv-lld

RISC-V port of LLVM Linker

riscv-edk2

Port of EDK2 implementation of UEFI to RISC-V. See documentation at:

riscv-gentoo

A port of Gentoo to RISC-V

riscv-zicond

The ISA specification for the ZiCondOps extension.

riscv-old-gcc

gcc+newlib and gcc+glibc toolchains

riscv-edk2-platforms

Port of EDK2 implementation of UEFI to RISC-V. See documentation at:

riscv-4th-workshop-tutorials

4th RISC-V Workshop Tutorials

riscv-zfinx

riscv-strace

RISC-V strace port

riscv-dejagnu

DejaGnu RISC-V port

documents

riscv.github.io

riscv-gentoo-infra

Infrastructure for building Gentoo for RISC-V

riscv-buildroot

RISC-V Buildroot

riscv-alt-fp

RISC-V Alternate FP Format

riscv-zacas

riscv-zacas created from docs-spec-template template

debug-taskgroup

Overview page for the RISC-V debug task group

riscv-weekly

RISC-V Weekly Community Update

riscv-libffi

RISC-V libffi port

riscv-buildbot-infra

The RISC-V buildbot infastructure

riscv-watchdog

riscv-crossdev

A RISC-V Port of Gentoo's Crossdev

riscv-svadu

The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.

riscv-zawrs

The repo will be used to hold the draft Zawrs (fast-track) extension and to make releases for reviews.

groups

RISC-V Technical Working Groups - charter, meeting minutes, planning documents

genz-on-riscv

riscv-sail-archive

riscv-time-compare

blockchain

Blockchain SIG Community

riscv-linux-infra

Scripts to help manager the RISC-V Linux codebase

riscv-state-enable

riscv-smcntrpmf

Cycle & Instret Privilege Mode Filtering Architecture Extension

riscv-indirect-csr-access

Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.

riscv-unix-class-platform-spec

RISC-V UNIX-class Platform Specification

riscv-count-overflow

mem-model

Private repo for the Memory Model Task Group

unified-discovery

automotive

Group administration repository for SIG: Automotive

riscv-CMOs-discuss

riscv-ras-terms-defs

The RAS Terms & Definitions specification define the terms and definitions for physical mechanisms starting from common ones from research and development to adapting the terms as needed.