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riscv-cores-list
RISC-V Cores, SoC platforms and SoCsriscv-linux
RISC-V Linux Portriscv-software-list
The RISC-V software tools list, as seen on riscv.orgriscv-qemu
QEMU with RISC-V (RV64G, RV32G) Emulation Supportriscv-gcc
riscv-wiki
educational-materials
Educational materials for RISC-Vrisc-v-getting-started-guide
The official RISC-V getting started guideriscv-go
riscv-code-size-reduction
riscv-binutils-gdb
RISC-V backports for binutils-gdb. Development is done upstream at the FSF.riscv-platform-specs
RISC-V Profiles and Platform Specificationriscv-newlib
RISC-V port of newlibriscv-musl
musl libc for RISC-VISA_Formal_Spec_Public_Review
Locus site for Public Review of Several RISC-V ISA Formal Specsriscv-glibc
RISC-V port of GNU's libcriscv-fesvr
RISC-V Frontend Serverriscv-poky
Port of the Yocto Project to the RISC-V ISAriscv-tee
riscv-clang
riscv-eabi-spec
Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.riscv-lld
RISC-V port of LLVM Linkerriscv-edk2
Port of EDK2 implementation of UEFI to RISC-V. See documentation at:riscv-gentoo
A port of Gentoo to RISC-Vriscv-zicond
The ISA specification for the ZiCondOps extension.riscv-old-gcc
gcc+newlib and gcc+glibc toolchainsriscv-edk2-platforms
Port of EDK2 implementation of UEFI to RISC-V. See documentation at:riscv-4th-workshop-tutorials
4th RISC-V Workshop Tutorialsriscv-zfinx
riscv-strace
RISC-V strace portriscv-dejagnu
DejaGnu RISC-V portdocuments
riscv.github.ioriscv-gentoo-infra
Infrastructure for building Gentoo for RISC-Vriscv-buildroot
RISC-V Buildrootriscv-alt-fp
RISC-V Alternate FP Formatriscv-zacas
riscv-zacas created from docs-spec-template templatedebug-taskgroup
Overview page for the RISC-V debug task groupriscv-weekly
RISC-V Weekly Community Updateriscv-libffi
RISC-V libffi portriscv-buildbot-infra
The RISC-V buildbot infastructureriscv-watchdog
riscv-crossdev
A RISC-V Port of Gentoo's Crossdevriscv-zawrs
The repo will be used to hold the draft Zawrs (fast-track) extension and to make releases for reviews.groups
RISC-V Technical Working Groups - charter, meeting minutes, planning documentsgenz-on-riscv
riscv-sail-archive
riscv-time-compare
blockchain
Blockchain SIG Communityriscv-linux-infra
Scripts to help manager the RISC-V Linux codebaseriscv-state-enable
riscv-smcntrpmf
Cycle & Instret Privilege Mode Filtering Architecture Extensionriscv-indirect-csr-access
Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.riscv-unix-class-platform-spec
RISC-V UNIX-class Platform Specificationriscv-count-overflow
mem-model
Private repo for the Memory Model Task Groupunified-discovery
automotive
Group administration repository for SIG: Automotiveriscv-CMOs-discuss
riscv-ras-terms-defs
The RAS Terms & Definitions specification define the terms and definitions for physical mechanisms starting from common ones from research and development to adapting the terms as needed.Love Open Source and this site? Check out how you can help us