RISC-V International - Archive (@riscvarchive)
  • Stars
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    4,708
  • Global Org. Rank 4,848 (Top 2 %)
  • Registered over 3 years ago
  • Most used languages
    C
    27.8 %
    Makefile
    27.8 %
    TeX
    19.4 %
    Shell
    5.6 %
    Python
    5.6 %
    Go
    2.8 %
    CSS
    2.8 %
    HTML
    2.8 %
    Coq
    2.8 %
    C++
    2.8 %

Top repositories

1

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs
830
star
2

riscv-linux

RISC-V Linux Port
C
606
star
3

riscv-software-list

The RISC-V software tools list, as seen on riscv.org
459
star
4

riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support
C
386
star
5

riscv-gcc

361
star
6

riscv-wiki

250
star
7

educational-materials

Educational materials for RISC-V
224
star
8

risc-v-getting-started-guide

The official RISC-V getting started guide
CSS
199
star
9

riscv-go

Go
155
star
10

riscv-code-size-reduction

Python
150
star
11

riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
C
148
star
12

riscv-platform-specs

RISC-V Profiles and Platform Specification
Makefile
111
star
13

riscv-newlib

RISC-V port of newlib
C
96
star
14

riscv-musl

musl libc for RISC-V
C
81
star
15

ISA_Formal_Spec_Public_Review

Locus site for Public Review of Several RISC-V ISA Formal Specs
73
star
16

riscv-glibc

RISC-V port of GNU's libc
70
star
17

riscv-fesvr

RISC-V Frontend Server
C
62
star
18

riscv-poky

Port of the Yocto Project to the RISC-V ISA
62
star
19

riscv-tee

Makefile
37
star
20

riscv-clang

27
star
21

riscv-eabi-spec

Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
26
star
22

riscv-lld

RISC-V port of LLVM Linker
C++
25
star
23

riscv-edk2

Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
C
22
star
24

riscv-gentoo

A port of Gentoo to RISC-V
20
star
25

riscv-zicond

The ISA specification for the ZiCondOps extension.
Makefile
19
star
26

riscv-old-gcc

gcc+newlib and gcc+glibc toolchains
18
star
27

riscv-edk2-platforms

Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
C
18
star
28

riscv-4th-workshop-tutorials

4th RISC-V Workshop Tutorials
C
14
star
29

riscv-zfinx

13
star
30

riscv-strace

RISC-V strace port
C
13
star
31

riscv-dejagnu

DejaGnu RISC-V port
TeX
12
star
32

documents

riscv.github.io
HTML
11
star
33

riscv-gentoo-infra

Infrastructure for building Gentoo for RISC-V
Shell
10
star
34

riscv-buildroot

RISC-V Buildroot
9
star
35

riscv-alt-fp

RISC-V Alternate FP Format
9
star
36

riscv-zacas

riscv-zacas created from docs-spec-template template
Makefile
9
star
37

debug-taskgroup

Overview page for the RISC-V debug task group
9
star
38

riscv-weekly

RISC-V Weekly Community Update
8
star
39

riscv-libffi

RISC-V libffi port
8
star
40

riscv-buildbot-infra

The RISC-V buildbot infastructure
Python
8
star
41

riscv-watchdog

Makefile
8
star
42

riscv-crossdev

A RISC-V Port of Gentoo's Crossdev
Shell
8
star
43

riscv-svadu

The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.
Makefile
7
star
44

riscv-zawrs

The repo will be used to hold the draft Zawrs (fast-track) extension and to make releases for reviews.
Makefile
6
star
45

groups

RISC-V Technical Working Groups - charter, meeting minutes, planning documents
6
star
46

genz-on-riscv

5
star
47

riscv-sail-archive

Coq
5
star
48

riscv-time-compare

TeX
4
star
49

blockchain

Blockchain SIG Community
3
star
50

riscv-linux-infra

Scripts to help manager the RISC-V Linux codebase
3
star
51

riscv-state-enable

TeX
3
star
52

riscv-smcntrpmf

Cycle & Instret Privilege Mode Filtering Architecture Extension
Makefile
3
star
53

riscv-indirect-csr-access

Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.
Makefile
3
star
54

riscv-unix-class-platform-spec

RISC-V UNIX-class Platform Specification
2
star
55

riscv-count-overflow

TeX
2
star
56

mem-model

Private repo for the Memory Model Task Group
TeX
1
star
57

unified-discovery

TeX
1
star
58

automotive

Group administration repository for SIG: Automotive
1
star
59

riscv-CMOs-discuss

Makefile
1
star
60

riscv-ras-terms-defs

The RAS Terms & Definitions specification define the terms and definitions for physical mechanisms starting from common ones from research and development to adapting the terms as needed.
TeX
1
star