riscvarchive/riscv-go

This repository has been archived on 04/Aug/2020
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riscvarchive/riscv-go

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The Go Programming Language

RISC-V Go Port

This repository is home of the RISC-V port of the Go programming language.

The upstream Go project can be found at https://github.com/golang/go.

This port has been upstreamed in Go 1.14. Please refer to upstream for all RISC-V development. This repository is outdated and archived.

Quick Start

Setup:

$ git clone https://review.gerrithub.io/riscv/riscv-go riscv-go
$ cd riscv-go
$ git checkout riscvdev  # RISC-V work happens on this branch
$ export GOROOT_BOOTSTRAP=/path/to/prebuilt/go/tree
$ export PATH="$(pwd)/misc/riscv:$(pwd)/bin:$PATH"
$ cd src
$ ./make.bash

Compile and run in qemu-riscv64 (which is expected to be in PATH):

$ GOARCH=riscv GOOS=linux go run ../riscvtest/add.go

Build:

$ GOARCH=riscv GOOS=linux go build ../riscvtest/add.go

Test:

Our basic tests are in the riscvtest directory:

$ cd ../riscvtest
$ go run run.go

If this exits without error, all is well!

QEMU

Spike plus pk support only a small subset of Linux syscalls and will not be capable of supporting the full Go runtime.

The RISC-V QEMU port supports a much wider set of syscalls with its "User Mode Simulation". See Method 2 in the QEMU README for instructions.

Contributing

All contributors must sign the upstream Contributor License Agreement, as this port will be merged into upstream Go upon completion.

Code review occurs via our GerritHub project, rather than via GitHub Pull Requests.

The upstream contribution guidelines include a basic overview of using Gerrit. While the upstream Go Gerrit server is different from ours, codereview.cfg will configure git-codereview to send CLs to GerritHub.

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-linux

RISC-V Linux Port

riscv-software-list

The RISC-V software tools list, as seen on riscv.org

riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support

riscv-gcc

riscv-wiki

educational-materials

Educational materials for RISC-V

risc-v-getting-started-guide

The official RISC-V getting started guide

riscv-code-size-reduction

riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.

riscv-platform-specs

RISC-V Profiles and Platform Specification

riscv-newlib

RISC-V port of newlib

riscv-musl

musl libc for RISC-V

ISA_Formal_Spec_Public_Review

Locus site for Public Review of Several RISC-V ISA Formal Specs

riscv-glibc

RISC-V port of GNU's libc

riscv-fesvr

RISC-V Frontend Server

riscv-poky

Port of the Yocto Project to the RISC-V ISA

riscv-tee

riscv-clang

riscv-eabi-spec

Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.

riscv-lld

RISC-V port of LLVM Linker

riscv-edk2

Port of EDK2 implementation of UEFI to RISC-V. See documentation at:

riscv-gentoo

A port of Gentoo to RISC-V

riscv-zicond

The ISA specification for the ZiCondOps extension.

riscv-old-gcc

gcc+newlib and gcc+glibc toolchains

riscv-edk2-platforms

Port of EDK2 implementation of UEFI to RISC-V. See documentation at:

riscv-4th-workshop-tutorials

4th RISC-V Workshop Tutorials

riscv-zfinx

riscv-strace

RISC-V strace port

riscv-dejagnu

DejaGnu RISC-V port

documents

riscv.github.io

riscv-gentoo-infra

Infrastructure for building Gentoo for RISC-V

riscv-buildroot

RISC-V Buildroot

riscv-alt-fp

RISC-V Alternate FP Format

riscv-zacas

riscv-zacas created from docs-spec-template template

debug-taskgroup

Overview page for the RISC-V debug task group

riscv-weekly

RISC-V Weekly Community Update

riscv-libffi

RISC-V libffi port

riscv-buildbot-infra

The RISC-V buildbot infastructure

riscv-watchdog

riscv-crossdev

A RISC-V Port of Gentoo's Crossdev

riscv-svadu

The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.

riscv-zawrs

The repo will be used to hold the draft Zawrs (fast-track) extension and to make releases for reviews.

groups

RISC-V Technical Working Groups - charter, meeting minutes, planning documents

genz-on-riscv

riscv-sail-archive

riscv-time-compare

blockchain

Blockchain SIG Community

riscv-linux-infra

Scripts to help manager the RISC-V Linux codebase

riscv-state-enable

riscv-smcntrpmf

Cycle & Instret Privilege Mode Filtering Architecture Extension

riscv-indirect-csr-access

Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.

riscv-unix-class-platform-spec

RISC-V UNIX-class Platform Specification

riscv-count-overflow

mem-model

Private repo for the Memory Model Task Group

unified-discovery

automotive

Group administration repository for SIG: Automotive

riscv-CMOs-discuss

riscv-ras-terms-defs

The RAS Terms & Definitions specification define the terms and definitions for physical mechanisms starting from common ones from research and development to adapting the terms as needed.