riscvarchive/educational-materials

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riscvarchive/educational-materials

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Educational materials for RISC-V

ALERT - THIS REPO IS ARCHIVED. If you would like to submit content, please send email to [email protected].

RISC-V Educational Materials

Interactive Online Courses

Author/University	Link	Access	Level	Platform	Content	Type
Introduction to RISC-V (LFD110x)	Link	Open	1	n/a	course	b,c,d,e
Building a RISC-V CPU Core (LFD111x)	Link	Open	2	HW	course	b,c,d,e
RISC-V Online Tutor	Link	Open	1-2	FPGA Access Provided	course	a,b,c,d,e,f
Udemy	Link	Paid	2	Sim	course	a,d
Maven Silicon	Link	Paid	2	Sim	HW/Sim	a,c,d,e,f

Online Materials

The following courses use RISC-V and share their materials online.

Author/University	Link	Access	Level	Platform	Content	Type
Oakland University	Link	Open	2	Unspecified	HW	f
UC Irvine	Link	Open	1	Sim	HW	a,f
MIT	Link	Open	2	Sim	HW	a,f
Boston University	Link	Open	1	Sim	HW	f
Boston University	Link	Open	1	Sim	HW	a,c,f
Redwood EDA	Link	Open	1-2	Makerchip	HW	c,e
EmulsiV Simulator	Working Instance, GitHub	Open (MPL2.0)	1	Sim	HW	e

Courses that use RISC-V

The following courses use RISC-V and share their syllabus.

Author/University	Link	Access	Level	Platform	Content	Type
University of Rochester	Link	Open	1	Unspecified	SW	f
University of Cambridge	Link	Open	2	FPGA	HW	f
University of Wisconsin-Madison	Link	Open	2	Sim	HW	f
Sarah Lawrence College	Link	Reg	2	Unspecified	SW	f
University of Virginia	Link	Reg	2	Unspecified	HW	f
Seminole State College of Florida	Link	Reg	1	Unspecified	HW	f
UC Santa Cruz	Link	Reg	2	Unspecified	HW	f
York University	Link	Reg	1	Unspecified	HW	c,f
New York University	Link	Reg	3	Unspecified	HW
Marmara University	Link	Reg	2	Sim	HW
Cornell College	Link	Open	2	Unspecified	tools
IIT Tirupati	Link	Reg	2	Unspecified	HW
Susquehanna University	Link	Reg	1	Unspecified	HW
MIT	Link	Open	2	FPGA	HW	a
Tsinghua University	Link	Open	3	Sim	tools	e
Rey Juan Carlos University (Spanish)	Link	Open	1	Sim/FPGA	SW
Redwood EDA/VLSI System Design	Link	Reg	1-2	VSD-IAT	Sim/HW	c,e
RVFPGA: Complete Course in Understanding Computer Architecture	Link	Open	1-3	FPGA	HW	a,c,e,f

Uncategorized

Needs to be checked again.

Author/University	Link	Access	Level	Platform	Content	Type
University of Texas	Link	Open	2	Unspecified	tools	f
Florida State University	Link	Open	2	Sim	HW	c,f
RISC-V 101 Article	Link	Reg	2	Unspecified	HW
IISc Bangalore	Link	Open	1	FPGA	HW	a,c,f
IISc Bangalore	Link	Reg	1	Unspecified	HW	c
IISc Bangalore - automated assembly gen	Link	Open	2	Sim	tools	e
Nanjing University (Chinese)	Link	Open	3	Linux native	SW	a
University of Siena	Link	Open	1	Sim	HW	e
University of Siena	Link	Open	1	Sim	HW	a
Nuclei System Technology (Chinese)	Link	Open	3	HummingBird E203	FPGA/HW/SW	a,c,d,f

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-linux

RISC-V Linux Port

riscv-software-list

The RISC-V software tools list, as seen on riscv.org

riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support

riscv-gcc

riscv-wiki

risc-v-getting-started-guide

The official RISC-V getting started guide

riscv-go

riscv-code-size-reduction

riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.

riscv-platform-specs

RISC-V Profiles and Platform Specification

riscv-newlib

RISC-V port of newlib

riscv-musl

musl libc for RISC-V

ISA_Formal_Spec_Public_Review

Locus site for Public Review of Several RISC-V ISA Formal Specs

riscv-glibc

RISC-V port of GNU's libc

riscv-fesvr

RISC-V Frontend Server

riscv-poky

Port of the Yocto Project to the RISC-V ISA

riscv-tee

riscv-clang

riscv-eabi-spec

Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.

riscv-lld

RISC-V port of LLVM Linker

riscv-edk2

Port of EDK2 implementation of UEFI to RISC-V. See documentation at:

riscv-gentoo

A port of Gentoo to RISC-V

riscv-zicond

The ISA specification for the ZiCondOps extension.

riscv-old-gcc

gcc+newlib and gcc+glibc toolchains

riscv-edk2-platforms

Port of EDK2 implementation of UEFI to RISC-V. See documentation at:

riscv-4th-workshop-tutorials

4th RISC-V Workshop Tutorials

riscv-zfinx

riscv-strace

RISC-V strace port

riscv-dejagnu

DejaGnu RISC-V port

documents

riscv.github.io

riscv-gentoo-infra

Infrastructure for building Gentoo for RISC-V

riscv-buildroot

RISC-V Buildroot

riscv-alt-fp

RISC-V Alternate FP Format

riscv-zacas

riscv-zacas created from docs-spec-template template

debug-taskgroup

Overview page for the RISC-V debug task group

riscv-weekly

RISC-V Weekly Community Update

riscv-libffi

RISC-V libffi port

riscv-buildbot-infra

The RISC-V buildbot infastructure

riscv-watchdog

riscv-crossdev

A RISC-V Port of Gentoo's Crossdev

riscv-svadu

The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.

riscv-zawrs

The repo will be used to hold the draft Zawrs (fast-track) extension and to make releases for reviews.

groups

RISC-V Technical Working Groups - charter, meeting minutes, planning documents

genz-on-riscv

riscv-sail-archive

riscv-time-compare

blockchain

Blockchain SIG Community

riscv-linux-infra

Scripts to help manager the RISC-V Linux codebase

riscv-state-enable

riscv-smcntrpmf

Cycle & Instret Privilege Mode Filtering Architecture Extension

riscv-indirect-csr-access

Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.

riscv-unix-class-platform-spec

RISC-V UNIX-class Platform Specification

riscv-count-overflow

mem-model

Private repo for the Memory Model Task Group

unified-discovery

automotive

Group administration repository for SIG: Automotive

riscv-CMOs-discuss

riscv-ras-terms-defs

The RAS Terms & Definitions specification define the terms and definitions for physical mechanisms starting from common ones from research and development to adapting the terms as needed.