Discover openhwgroup/core-v-xif Open Source project

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Language SystemVerilog
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Created over 3 years ago
Updated 6 months ago

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RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Assembly

2,230

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

SystemVerilog

941

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Assembly

430

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

SystemVerilog

426

force-riscv

Instruction Set Generator initially contributed by Futurewei

C++

259

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

SystemVerilog

251

cv32e40x

4 stage, in-order, compute RISC-V core based on the CV32E40P

SystemVerilog

210

core-v-cores

CORE-V Family of RISC-V Cores

202

programs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

HTML

187

core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

SystemVerilog

165

cv32e40s

4 stage, in-order, secure RISC-V core based on the CV32E40P

SystemVerilog

128

cva6-sdk

CVA6 SDK containing RISC-V tools and Buildroot

Makefile

cva5

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

SystemVerilog

cv-hpdcache

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

SystemVerilog

cv32e41p

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

SystemVerilog

corev-gcc

C++

core-v-mcu-uvm

CORE-V MCU UVM Environment and Test Bench

SystemVerilog

openhwgroup.org

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

HTML

core-v-sw

Main Repo for the OpenHW Group Software Task Group

riscv_vm

Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board

Shell

core-v-sdk

Java

core-v-mcu-devkit

This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.

HTML

corev-llvm-project

tristan-isolde-unified-access-page

Unified Access Page for the TRISTAN project

HTML

riscv-ovpsim-corev

cv32e40x-dv

CV32E40X Design-Verification environment

Assembly

corev-binutils-gdb

core-v-mcu-cli-test

Eclipse/FreeRTOS/core-v-mcu example program

core-v-ide-cdt

Java

cva6-platform

CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform

advanced-riscv-verification-methodologies

Advanced Verification Methodologies for RISC-V and related IP

SystemVerilog

cv-hpdcache-verif

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.

SystemVerilog

obi

Repository that maintain the OpenBus Interface spec

core-v-freertos

cv-mesh

u-boot

Unofficial development fork of U-Boot

cvw-arch-verif

The purpose of the repo is to support CORE-V Wally architectural verification

SystemVerilog

core-v-freertos-kernel

downloads.openhwgroup.org

SCSS

osdforum.org

The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.

HTML

openhwgroup/core-v-xif

openhwgroup

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