• This repository has been archived on 24/Nov/2023
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  • Rank 930,752 (Top 19 %)
  • Language SystemVerilog
  • License
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  • Created over 3 years ago
  • Updated over 1 year ago

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Repository Details

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

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