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cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linuxcv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platformcvfpu
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.force-riscv
Instruction Set Generator initially contributed by Futureweicvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40Pcore-v-cores
CORE-V Family of RISC-V Coresprograms
Documentation for the OpenHW Group's set of CORE-V RISC-V corescore-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.cv32e40s
4 stage, in-order, secure RISC-V core based on the CV32E40Pcva6-sdk
CVA6 SDK containing RISC-V tools and Buildrootcore-v-xif
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensionscva5
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.cv-hpdcache
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV corescv32e41p
4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentionscorev-gcc
core-v-sdk
core-v-sw
Main Repo for the OpenHW Group Software Task Groupopenhwgroup.org
OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.core-v-mcu-uvm
CORE-V MCU UVM Environment and Test Benchriscv_vm
Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA boardcore-v-mcu-devkit
This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.corev-llvm-project
riscv-ovpsim-corev
cv32e40x-dv
CV32E40X Design-Verification environmentcorev-binutils-gdb
core-v-mcu-cli-test
Eclipse/FreeRTOS/core-v-mcu example programcore-v-ide-cdt
cva6-platform
CVA6-platform is a multicore CVA6 with CV-MESH software and regression platformadvanced-riscv-verification-methodologies
Advanced Verification Methodologies for RISC-V and related IPobi
Repository that maintain the OpenBus Interface speccore-v-freertos
cv-mesh
u-boot
Unofficial development fork of U-Bootcore-v-freertos-kernel
downloads.openhwgroup.org
downloads.openhwgroup.orgosdforum.org
The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.cvw-arch-verif
The purpose of the repo is to support CORE-V Wally architectural verificationLove Open Source and this site? Check out how you can help us