openhwgroup/programs

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openhwgroup/programs

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Documentation for the OpenHW Group's set of CORE-V RISC-V cores

programs

Program and project level documentation for all of OpenHW Group's projects including CORE-V RISC-V cores.

Directory contents...

TWG

Technical Working Group meeting minutes and presentations.

TG

Task Group monthly reports, meeting minutes and presentations. This comprises

cores-task-group

hw-task-group

verification-task-group

Currently the sw-task-grouped is tracked in the core-v-sw repo.

OpenHW-Project-Descriptions-and-Plans

This contains one directory per OpenHW project. Each directory should contain gate materials for the project (Project Concept, Project Launch, Plan Approve, and Project Freeze) Readers can use this information to see all OpenHW projects at a glance

OpenHW-dashboard

This contains a markdown file with project dashboard information for OpenHW. This file is linked from the OpenHW website.

process

This contains OpenHW process and template documents, such as gate templates and RTL Freeze template.

Attendance-tracking

This contains attendance tracking for all OpenHW meetings.

Issues and Troubleshooting

If you find any problems or issues with the structure or content of this repo, please check out the issue tracker and create a new issue if your problem is not yet tracked.

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

force-riscv

Instruction Set Generator initially contributed by Futurewei

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

cv32e40x

4 stage, in-order, compute RISC-V core based on the CV32E40P

core-v-cores

CORE-V Family of RISC-V Cores

core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

cv32e40s

4 stage, in-order, secure RISC-V core based on the CV32E40P

cva6-sdk

CVA6 SDK containing RISC-V tools and Buildroot

core-v-xif

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

cva5

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

cv-hpdcache

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

cv32e41p

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

corev-gcc

core-v-mcu-uvm

CORE-V MCU UVM Environment and Test Bench

openhwgroup.org

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

core-v-sw

Main Repo for the OpenHW Group Software Task Group

riscv_vm

Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board

core-v-sdk

core-v-mcu-devkit

This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.

corev-llvm-project

tristan-isolde-unified-access-page

Unified Access Page for the TRISTAN project

riscv-ovpsim-corev

cv32e40x-dv

CV32E40X Design-Verification environment

corev-binutils-gdb

core-v-mcu-cli-test

Eclipse/FreeRTOS/core-v-mcu example program

core-v-ide-cdt

cva6-platform

CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform

advanced-riscv-verification-methodologies

Advanced Verification Methodologies for RISC-V and related IP

cv-hpdcache-verif

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.

obi

Repository that maintain the OpenBus Interface spec

core-v-freertos

cv-mesh

u-boot

Unofficial development fork of U-Boot

cvw-arch-verif

The purpose of the repo is to support CORE-V Wally architectural verification

core-v-freertos-kernel

downloads.openhwgroup.org

downloads.openhwgroup.org

osdforum.org

The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.