• Stars
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    8
  • Rank 2,041,472 (Top 42 %)
  • Language
    Scala
  • License
    Apache License 2.0
  • Created over 4 years ago
  • Updated over 2 years ago

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Repository Details

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

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