merledu/Pyverilog-sv2v

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merledu/Pyverilog-sv2v

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Pyverilog-sv2v is converting systemverilog code to verilog code. The converted script in verilog is used in pyverilog and pyverilog_toolbox that does not correspond to the systemverilog.

nucleusrv

NucleusRV - A 32-bit 5 staged pipelined risc-v core.

azadi-soc

Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

TileLink

TileLink Uncached Lightweight (TL-UL) implementation on Chisel.

OpenTCAM

An open-source Ternary Content Addressable Memory (TCAM) compiler.

SIngle-Cycle-RISC-V-In-Verilog

This repository contains the verilog code files of Single Cycle RISC-V architecture

caravan

A caravan equipped with API for creating bus protocols in Chisel with ease.

vaquita

Google-Summer-of-Code

Project ideas list for Google Summer of Code.

symbiflow-magic

This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.

Scala-Chisel-Learning-Journey

This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks related to it.

Jupyter Notebook

100DaysOfCHISEL

100 Days of CHISEL inspired by 100DaysOfRTL

magma-si

Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL

Riscv-Single-Cycle-Cores

This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Programming w/ Scala

azadi

[Deprecated] Azadi is an SoC with 32 bit RISC-V CPU core.

OpenLane_Workshop

This repository contains the training material for Tapeout Pakistan OpenLane workshop conducted by MERL-UIT.

buraq_mini

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

Single-Cycle-CPU

This repository contains the implementation of a single cycle CPU based on RISC-V ISA and implemented on CHISEL Hardware Construction Language (HDL)

rv-thunder

RISC-V 32-bit CPU written in amaranth (python-lib)

picofoxy

Pipelined In-order Core for Artix-7 Arty-35T board

Burq-Suite

An All in one RISC-V Suite.

azadi-verify

This repository contains tests (in C and assembly both), benchmarks and the test-benches for the verification of Azadi SoC.

Shaheen

A minimal System on a Chip (SoC) based on RISC-V compute which focuses on IoT domain.

common_peripheral_vips

Ibtida

A basic System on a Chip (SoC) based on the Buraq core for the Internet of Things (IoT).

caravel_azadi_soc_iii_dft

This project is the extended version of Azadi-SoC, which includes all of the peripherals which were in Azadi-II and few more this time, which were not stable at the time of Azadi-II. The Azadi-III includes the following peripherals. PWM 2-Channel, OpenRAM 1KB x 4 for ICCM 1KB x 4 for DCCM Ibex core(named as brq_core) FPU (single-precision) TileLink (UL) UART QSPI SPI GPIOs Design Goals: Azadi-III is aimed to extend the base ibex core(RV32IMC) with a fully functional single precision floating point unit and RISCV compliant debug module for on chip debugging and some standard peripherals for communicating with other devices. all these modules will be interlinked using standard Tilelink Bus protocol. The project aims at adding DFT support to Caravel chip to enable post fabrication testing using Automatic Testing Equipment (ATE). Scan chain is applied to making a design testable , observable and controllable after it has been manufactured.

SoC-Now

An open source Mini SoC Generator which will generate SoC based on parameters.

Self-Checking-Tests

LibertyParser

It is a liberty File Parser which is exporting the data from liberty file into csv file and plotting the data for better understading

cachefy

CHISEL API for plug n play connection of Caches in CHISEL designs

Rev-Soc

Buraq-compressed-assembler

This is the compressed assembler for RISC-V.

Bitstream-Chef

verification_training

verification training

jigsaw

A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).

common_peripheral_ips

This repository contains generic peripheral IPs. These IPs can be used as memory mapped device with various bus interfaces like, Tilelink, AXI, AXI-Lite and APB.

RISC-V-single-cycle-core-Logisim

This repository is for RISC-V single cycle core

briscv-merl

This repo holds the BRISC-V cores, used for the MERL APR training.

nova

An opensource ariane based SoC on aws-fpga

zeusic-v

RISC-V based Neuromorphic Processor for accelerating Spiking Neural Networks

Core-SweRV-EH2--verilog

azadi-sdk

Software Developement Kit (SDK) for Azadi-SoC

caravel_soc_now

TENNA

TENNA: Tiny Embedded Neural Network Accelerator

Tapeout_Pakistan_Training

Tcam

This repository contains SRAm based TCAM (ternary content addrerssable memory) IP.

caravel_Ghazi_SoC_II

KyberQuanta

A Kyber768-90's Hardware Accelerator.

Lib-Analyzer

Lib Analyzer is an application which is used to analyze the cells in the liberty files.

tinyML-with-TensorFlow-Lite

wenquxing22A

Clone of wangjie1450/Wenquxing22A modified for research purpose

xodus

RV32-I 5 Stage Pipelined Core implemented in CHISEL HDL

Quad_SPI

Quad SPI interface for the micron flash available on arty a7-35t FPGA board

SoC-Now-Verification

ideas-2022

Ideas for the future

Merl-UIT-Simulator

Chisel-Generated-Verilog-on-FPGA

Shaheen-Core

This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.

porting-docs

This repo contains multiple documentations related to linux porting on RISC-V. Also, running TFLite Models with Zephyr RTOS on RENODE upon RISC-V.

SoC-Now-Generator

An open source Mini SoC Generator which will generate SoC based on parameters.

Porting-Progress

rv_fpu_wrapper

A wrapper use to connect open-source FPU with RISC-V CPU.

ML-AI-Learning-Journey

In this repository there are multiple projects related to Artificial Intelligence.

5-Stage-Pipeline-RISC-V-Architecture-in-Verilog

This repository contains the verilog cde files of 5 stage Pipeline RISC-V architecture

BURQ-IDE

This Repository Contains Source Code for the Burq-ide project

azadi_apr

This repo hold all of the source files and apr file for Azadi SoC.

OpenFabric

Open source generator for creating customisable bus topologies (Point-to-point, Shared Bus, CrossBar Switch) based on the bus protocol type provided by the user (AHB, Wishbone, TileLink)

Athestia

Clean slate application using NDN with Dilithium to enhance security in future internet technology

oxygen

A RISC-V Simulator

SRAM_based_TCAM

This project is tied as an accelerator to the management SoC. It mimic the functionality of TCAM using SRAM. We will utilize OpenRAM to generate SRAM-based TCAM.