Micro Electronics Research Laboratory (@merledu)
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Top repositories

1

nucleusrv

NucleusRV - A 32-bit 5 staged pipelined risc-v core.
C
59
star
2

azadi-soc

Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
SystemVerilog
26
star
3

TileLink

TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
Scala
21
star
4

OpenTCAM

An open-source Ternary Content Addressable Memory (TCAM) compiler.
Python
19
star
5

SIngle-Cycle-RISC-V-In-Verilog

This repository contains the verilog code files of Single Cycle RISC-V architecture
Verilog
15
star
6

caravan

A caravan equipped with API for creating bus protocols in Chisel with ease.
Scala
12
star
7

vaquita

Scala
12
star
8

Google-Summer-of-Code

Project ideas list for Google Summer of Code.
11
star
9

symbiflow-magic

This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.
Makefile
10
star
10

Scala-Chisel-Learning-Journey

This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks related to it.
Jupyter Notebook
9
star
11

100DaysOfCHISEL

100 Days of CHISEL inspired by 100DaysOfRTL
Scala
9
star
12

magma-si

Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL
Scala
8
star
13

Riscv-Single-Cycle-Cores

This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Programming w/ Scala
Scala
8
star
14

azadi

[Deprecated] Azadi is an SoC with 32 bit RISC-V CPU core.
SystemVerilog
8
star
15

OpenLane_Workshop

This repository contains the training material for Tapeout Pakistan OpenLane workshop conducted by MERL-UIT.
Verilog
8
star
16

buraq_mini

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)
Scala
8
star
17

Single-Cycle-CPU

This repository contains the implementation of a single cycle CPU based on RISC-V ISA and implemented on CHISEL Hardware Construction Language (HDL)
TeX
8
star
18

rv-thunder

RISC-V 32-bit CPU written in amaranth (python-lib)
Verilog
7
star
19

picofoxy

Pipelined In-order Core for Artix-7 Arty-35T board
Scala
7
star
20

Burq-Suite

An All in one RISC-V Suite.
JavaScript
5
star
21

azadi-verify

This repository contains tests (in C and assembly both), benchmarks and the test-benches for the verification of Azadi SoC.
Assembly
5
star
22

Shaheen

A minimal System on a Chip (SoC) based on RISC-V compute which focuses on IoT domain.
Verilog
5
star
23

common_peripheral_vips

SystemVerilog
4
star
24

Pyverilog-sv2v

Pyverilog-sv2v is converting systemverilog code to verilog code. The converted script in verilog is used in pyverilog and pyverilog_toolbox that does not correspond to the systemverilog.
Python
4
star
25

Ibtida

A basic System on a Chip (SoC) based on the Buraq core for the Internet of Things (IoT).
Verilog
4
star
26

caravel_azadi_soc_iii_dft

This project is the extended version of Azadi-SoC, which includes all of the peripherals which were in Azadi-II and few more this time, which were not stable at the time of Azadi-II. The Azadi-III includes the following peripherals. PWM 2-Channel, OpenRAM 1KB x 4 for ICCM 1KB x 4 for DCCM Ibex core(named as brq_core) FPU (single-precision) TileLink (UL) UART QSPI SPI GPIOs Design Goals: Azadi-III is aimed to extend the base ibex core(RV32IMC) with a fully functional single precision floating point unit and RISCV compliant debug module for on chip debugging and some standard peripherals for communicating with other devices. all these modules will be interlinked using standard Tilelink Bus protocol. The project aims at adding DFT support to Caravel chip to enable post fabrication testing using Automatic Testing Equipment (ATE). Scan chain is applied to making a design testable , observable and controllable after it has been manufactured.
Verilog
4
star
27

SoC-Now

An open source Mini SoC Generator which will generate SoC based on parameters.
Python
4
star
28

Self-Checking-Tests

C
3
star
29

LibertyParser

It is a liberty File Parser which is exporting the data from liberty file into csv file and plotting the data for better understading
Python
3
star
30

cachefy

CHISEL API for plug n play connection of Caches in CHISEL designs
Scala
3
star
31

Rev-Soc

SystemVerilog
3
star
32

Buraq-compressed-assembler

This is the compressed assembler for RISC-V.
Python
3
star
33

Bitstream-Chef

HTML
3
star
34

verification_training

verification training
SystemVerilog
3
star
35

jigsaw

A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).
Scala
3
star
36

common_peripheral_ips

This repository contains generic peripheral IPs. These IPs can be used as memory mapped device with various bus interfaces like, Tilelink, AXI, AXI-Lite and APB.
SystemVerilog
3
star
37

RISC-V-single-cycle-core-Logisim

This repository is for RISC-V single cycle core
2
star
38

briscv-merl

This repo holds the BRISC-V cores, used for the MERL APR training.
Verilog
2
star
39

nova

An opensource ariane based SoC on aws-fpga
VHDL
2
star
40

zeusic-v

RISC-V based Neuromorphic Processor for accelerating Spiking Neural Networks
2
star
41

Core-SweRV-EH2--verilog

Verilog
2
star
42

azadi-sdk

Software Developement Kit (SDK) for Azadi-SoC
C
2
star
43

caravel_soc_now

Verilog
2
star
44

TENNA

TENNA: Tiny Embedded Neural Network Accelerator
2
star
45

Tapeout_Pakistan_Training

2
star
46

Tcam

This repository contains SRAm based TCAM (ternary content addrerssable memory) IP.
2
star
47

caravel_Ghazi_SoC_II

Verilog
2
star
48

KyberQuanta

A Kyber768-90's Hardware Accelerator.
2
star
49

Lib-Analyzer

Lib Analyzer is an application which is used to analyze the cells in the liberty files.
Python
2
star
50

tinyML-with-TensorFlow-Lite

1
star
51

wenquxing22A

Clone of wangjie1450/Wenquxing22A modified for research purpose
Verilog
1
star
52

xodus

RV32-I 5 Stage Pipelined Core implemented in CHISEL HDL
Scala
1
star
53

Quad_SPI

Quad SPI interface for the micron flash available on arty a7-35t FPGA board
SystemVerilog
1
star
54

SoC-Now-Verification

Verilog
1
star
55

ideas-2022

Ideas for the future
1
star
56

Merl-UIT-Simulator

JavaScript
1
star
57

Chisel-Generated-Verilog-on-FPGA

Verilog
1
star
58

Shaheen-Core

This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.
TeX
1
star
59

porting-docs

This repo contains multiple documentations related to linux porting on RISC-V. Also, running TFLite Models with Zephyr RTOS on RENODE upon RISC-V.
1
star
60

SoC-Now-Generator

An open source Mini SoC Generator which will generate SoC based on parameters.
Verilog
1
star
61

Porting-Progress

1
star
62

rv_fpu_wrapper

A wrapper use to connect open-source FPU with RISC-V CPU.
1
star
63

ML-AI-Learning-Journey

In this repository there are multiple projects related to Artificial Intelligence.
Python
1
star
64

5-Stage-Pipeline-RISC-V-Architecture-in-Verilog

This repository contains the verilog cde files of 5 stage Pipeline RISC-V architecture
Verilog
1
star
65

BURQ-IDE

This Repository Contains Source Code for the Burq-ide project
Python
1
star
66

azadi_apr

This repo hold all of the source files and apr file for Azadi SoC.
Verilog
1
star
67

OpenFabric

Open source generator for creating customisable bus topologies (Point-to-point, Shared Bus, CrossBar Switch) based on the bus protocol type provided by the user (AHB, Wishbone, TileLink)
1
star
68

Athestia

Clean slate application using NDN with Dilithium to enhance security in future internet technology
1
star
69

oxygen

A RISC-V Simulator
Python
1
star
70

SRAM_based_TCAM

This project is tied as an accelerator to the management SoC. It mimic the functionality of TCAM using SRAM. We will utilize OpenRAM to generate SRAM-based TCAM.
1
star