Discover merledu/SoC-Now-Generator Open Source project

TileLink Uncached Lightweight (TL-UL) implementation on Chisel.

TileLink

An open-source Ternary Content Addressable Memory (TCAM) compiler.

OpenTCAM

This repository contains the verilog code files of Single Cycle RISC-V architecture

SIngle-Cycle-RISC-V-In-Verilog

A caravan equipped with API for creating bus protocols in Chisel with ease.

caravan

vaquita

Project ideas list for Google Summer of Code.

Google-Summer-of-Code

symbiflow-magic

This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.

Makefile

Scala-Chisel-Learning-Journey

This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks related to it.

Jupyter Notebook

100DaysOfCHISEL

100 Days of CHISEL inspired by 100DaysOfRTL

Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL

magma-si

This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Programming w/ Scala

Riscv-Single-Cycle-Cores

[Deprecated] Azadi is an SoC with 32 bit RISC-V CPU core.

azadi

This repository contains the training material for Tapeout Pakistan OpenLane workshop conducted by MERL-UIT.

OpenLane_Workshop

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

buraq_mini

This repository contains the implementation of a single cycle CPU based on RISC-V ISA and implemented on CHISEL Hardware Construction Language (HDL)

Single-Cycle-CPU

TeX

rv-thunder

RISC-V 32-bit CPU written in amaranth (python-lib)

Pipelined In-order Core for Artix-7 Arty-35T board

picofoxy

An All in one RISC-V Suite.

Burq-Suite

JavaScript

azadi-verify

This repository contains tests (in C and assembly both), benchmarks and the test-benches for the verification of Azadi SoC.

Assembly

Shaheen

A minimal System on a Chip (SoC) based on RISC-V compute which focuses on IoT domain.

common_peripheral_vips

Pyverilog-sv2v is converting systemverilog code to verilog code. The converted script in verilog is used in pyverilog and pyverilog_toolbox that does not correspond to the systemverilog.

Pyverilog-sv2v

A basic System on a Chip (SoC) based on the Buraq core for the Internet of Things (IoT).

Ibtida

This project is the extended version of Azadi-SoC, which includes all of the peripherals which were in Azadi-II and few more this time, which were not stable at the time of Azadi-II. The Azadi-III includes the following peripherals. PWM 2-Channel, OpenRAM 1KB x 4 for ICCM 1KB x 4 for DCCM Ibex core(named as brq_core) FPU (single-precision) TileLink (UL) UART QSPI SPI GPIOs Design Goals: Azadi-III is aimed to extend the base ibex core(RV32IMC) with a fully functional single precision floating point unit and RISCV compliant debug module for on chip debugging and some standard peripherals for communicating with other devices. all these modules will be interlinked using standard Tilelink Bus protocol. The project aims at adding DFT support to Caravel chip to enable post fabrication testing using Automatic Testing Equipment (ATE). Scan chain is applied to making a design testable , observable and controllable after it has been manufactured.

caravel_azadi_soc_iii_dft

An open source Mini SoC Generator which will generate SoC based on parameters.

SoC-Now

It is a liberty File Parser which is exporting the data from liberty file into csv file and plotting the data for better understading

Self-Checking-Tests

LibertyParser

CHISEL API for plug n play connection of Caches in CHISEL designs

cachefy

Rev-Soc

This is the compressed assembler for RISC-V.

Buraq-compressed-assembler

Bitstream-Chef

HTML

verification_training

verification training

A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).

jigsaw

This repository contains generic peripheral IPs. These IPs can be used as memory mapped device with various bus interfaces like, Tilelink, AXI, AXI-Lite and APB.

common_peripheral_ips

This repository is for RISC-V single cycle core

RISC-V-single-cycle-core-Logisim

briscv-merl

This repo holds the BRISC-V cores, used for the MERL APR training.

An opensource ariane based SoC on aws-fpga

nova

VHDL

zeusic-v

RISC-V based Neuromorphic Processor for accelerating Spiking Neural Networks

Core-SweRV-EH2--verilog

Software Developement Kit (SDK) for Azadi-SoC

azadi-sdk

caravel_soc_now

TENNA: Tiny Embedded Neural Network Accelerator

TENNA

Tapeout_Pakistan_Training

Tcam

This repository contains SRAm based TCAM (ternary content addrerssable memory) IP.

caravel_Ghazi_SoC_II

A Kyber768-90's Hardware Accelerator.

KyberQuanta

Lib-Analyzer

Lib Analyzer is an application which is used to analyze the cells in the liberty files.

Clone of wangjie1450/Wenquxing22A modified for research purpose

tinyML-with-TensorFlow-Lite

wenquxing22A

RV32-I 5 Stage Pipelined Core implemented in CHISEL HDL

xodus

Quad SPI interface for the micron flash available on arty a7-35t FPGA board

Quad_SPI

SoC-Now-Verification

ideas-2022

Merl-UIT-Simulator

Chisel-Generated-Verilog-on-FPGA

This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.

Shaheen-Core

TeX

porting-docs

This repo contains multiple documentations related to linux porting on RISC-V. Also, running TFLite Models with Zephyr RTOS on RENODE upon RISC-V.

Porting-Progress

rv_fpu_wrapper

A wrapper use to connect open-source FPU with RISC-V CPU.

ML-AI-Learning-Journey

In this repository there are multiple projects related to Artificial Intelligence.

This repository contains the verilog cde files of 5 stage Pipeline RISC-V architecture

5-Stage-Pipeline-RISC-V-Architecture-in-Verilog

This Repository Contains Source Code for the Burq-ide project

BURQ-IDE

This repo hold all of the source files and apr file for Azadi SoC.

azadi_apr

Open source generator for creating customisable bus topologies (Point-to-point, Shared Bus, CrossBar Switch) based on the bus protocol type provided by the user (AHB, Wishbone, TileLink)

OpenFabric

Athestia

Clean slate application using NDN with Dilithium to enhance security in future internet technology

oxygen

A RISC-V Simulator