• Stars
    star
    255
  • Rank 159,729 (Top 4 %)
  • Language Verilog
  • License
    Apache License 2.0
  • Created about 3 years ago
  • Updated 7 months ago

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

Caravel Harness

GitHub license - Apache 2.0 ReadTheDocs Badge - https://caravel-harness.rtfd.io Travis Badge - https://travis-ci.org/efabless/caravel

NOTE:

Documentation for this project is being updated to reflect the changes for the new redesigned version of Caravel.

Table of contents

Overview

Caravel is a template SoC for Efabless Open MPW and chipIgnite shuttles based on the Sky130 node from SkyWater Technologies. The current SoC architecture is given below.

docs/source/_static/caravel_block_diagram.jpg

Datasheet and detailed documentation exist here

Caravel Architecture

Caravel is composed of the harness frame plus two wrappers for drop-in modules for the management area and user project area.

Harness Definition

The harness itself contains the clocking module, DLL, user ID, housekeeping SPI, POR, and GPIO control.

GPIO handling moved out of management SoC and into SPI. SPI gets a wishbone interface; the management SoC talks to the SPI through wishbone, not by taking over the 4-pin SPI interface.

A new block like the ID has the mode at power-up for each GPIO. Can be configured with a text file. SPI pins are fixed for operation on startup.

On power-up, the SPI automatically configures the GPIO. Manual load is possible from both the SPI and from the wishbone bus.

All functions within the harness but outside the management SoC are incorporated into one large module called "housekeeping". This includes a number of registers for all the included functions, with a "front door" SPI interface connected to the padframe through GPIO pins 1 to 4, and a "back door" wishbone interface connected to the management SoC. The management Soc reserves the memory block at 0x26000000 for the housekeeping module. The housekeeping module exchanges data with the management SoC via an interface that uses the byte- wide SPI register data. A small state machine reads four contiguous wishbone addresses and an address decoder determines the corresponding SPI register. The state machine stalls the SoC until all four bytes have been handled before returning the acknowledge signal.

Management Area

The management area is a drop-in module implemented as a separate repo. It typically includes a RISC-V based SoC that includes a number of peripherals like timers, uart, and gpio. The management area runs firmware that can be used to:

  • Configure User Project I/O pads
  • Observe and control User Project signals (through on-chip logic analyzer probes)
  • Control the User Project power supply

The management area implements SRAM for the management SoC.

The default instantiation for the management core can be found here . See documentation of the management core for further details.

User Project Area

This is the user space. It has a limited silicon area 2.92mm x 3.52mm as well as a fixed number of I/O pads 38 and power pads 4.

The user space has access to the following utilities provided by the management SoC:

  • 38 IO Ports
  • 128 Logic analyzer probes
  • Wishbone port connection to the management SoC wishbone bus.

Quick Start for User Projects

Your area is the full user space, so feel free to add your project there or create a different macro and harden it separately then insert it into the user_project_wrapper for digital projects or insert it into user_project_analog_wrapper for analog projects.

Digital User Project

If you are building a digital project for the user space, check a sample project at caravel_user_project.

If you will use OpenLANE to harden your design, go through the instructions in this README.

Digital user projects should adhere the following requirements:

Analog User Project

If you are building an analog project for the user space, check a sample project at caravel_user_project_analog.

Analog user projects should adhere the following requirements:

  • Top module is named user_analog_project_wrapper
  • The user_analog_project_wrapper uses the empty analog wrapper.
  • The user_analog_project_wrapper adheres to the same pin order and placement of the empty analog wrapper.

IMPORTANT

Please make sure to run make compress before committing anything to your repository. Avoid having 2 versions of the gds/user_project_wrapper.gds one compressed and the other not compressed.

For information on tooling and versioning, please refer to tool-versioning.rst.


Required Directory Structure

  • gds/ : includes all the gds files used or produced from the project.
  • def : includes all the def files used or produced from the project.
  • lef/ : includes all the lef files used or produced from the project.
  • mag/ : includes all the mag files used or produced from the project.
  • maglef : includes all the maglef files used or produced from the project.
  • spi/lvs/ : includes all the spice files used or produced from the project.
  • verilog/dv : includes all the simulation test benches and how to run them.
  • verilog/gl/ : includes all the synthesized/elaborated netlists.
  • verilog/rtl : includes all the Verilog RTLs and source files.
  • openlane/<macro>/ : includes all configuration files used to run openlane on your project.
  • info.yaml: includes all the info required in this example. Please make sure that you are pointing to an elaborated caravel netlist as well as a synthesized gate-level-netlist for the user_project_wrapper

NOTE:

If you're using openlane to harden your design, the verilog/gl def/ lef/ gds/ mag maglef directories should be automatically populated by openlane.

Additional Material

MPW Two

MPW One

Check mpw-one-final for the caravel used for the mpw-one tapeout.

> ⚠️ You don't need to integrate your design with Caravel GDS for MPW two. Running make ship is no longer required.

More Repositories

1

raven-picorv32

Silicon-validated SoC implementation of the PicoSoc/PicoRV32
Verilog
254
star
2

openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture
Python
205
star
3

caravel_user_project

https://caravel-user-project.readthedocs.io
Verilog
165
star
4

caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Verilog
133
star
5

chipignite-resources

63
star
6

volare

Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
Python
63
star
7

foss-asic-tools

FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already installed and ready to use.
Tcl
59
star
8

clear

Verilog
57
star
9

cace

Circuit Automatic Characterization Engine
Python
45
star
10

caravel_user_project_analog

Verilog
42
star
11

sky130_sram_macros_old

SourcePawn
35
star
12

mpw_precheck

Python
34
star
13

chipcraft---mest-course

TL-Verilog
29
star
14

caravel_board

C
28
star
15

proton

Perl
28
star
16

caravel_mgmt_soc_litex

https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
Verilog
25
star
17

sky130_klayout_pdk

Skywaters 130nm Klayout PDK
Python
17
star
18

caravel-lite

Verilog
16
star
19

ipm

Open-source IPs Package Manager (IPM)
Python
14
star
20

raptor

Arm Cortex-M0 based Customizable SoC for IoT Applications
Assembly
12
star
21

raptor_soc_template

Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
Verilog
12
star
22

clear_old

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.
Verilog
10
star
23

ravenna

32-bit RISC-V microcontroller
C
9
star
24

caravel-gf180mcu

This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
Verilog
8
star
25

nix-eda

Nix derivations for EDA tools
Nix
6
star
26

EF_PSRAM_CTRL

A Quad I/O SPI Pseudo Static RAM (PSRAM) Controller
Verilog
6
star
27

openrcx-calibration

Verilog
5
star
28

timer-tutorial

Source files for the timer-tutorial
Tcl
4
star
29

BusWrap

Python
4
star
30

Caravel_on_FPGA

Verilog
4
star
31

openfpga-2

Verilog
3
star
32

EF_UART

Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
Verilog
3
star
33

arduino-greenpak-shield

Shield for the GreenPak SLG468X chipset
Python
3
star
34

caravel_mini

Multi-Project Support for Caravel
Verilog
3
star
35

EF_TCC32

A 32-bit Timer/Counter/Capture Soft IP (Verilog)
Verilog
3
star
36

EF_LDOR1V8

Open Source, 3.3 V to 1.8 V, 100 mA Full Regulator
Python
3
star
37

openlane-ci-designs

Verilog
3
star
38

EF_SRAM_1024x32

Verilog
3
star
39

caravel_user_mini

Verilog
2
star
40

strive

Python
2
star
41

caravel_SI_testing

C
2
star
42

nm

Verilog
2
star
43

nldiff

Simple netlist comparison utility
Python
2
star
44

caravel_ibex

An example project that utilizes caravel user space for an ibex based SoC
Verilog
2
star
45

dockerized-verification-setup

This is a dockerized tool chain for running verilog DV customized for the sky130A-based projects.
Dockerfile
2
star
46

sram_macro_16KB

Verilog
2
star
47

sak-deprecated

SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA
Python
2
star
48

EF_UVM

Python
2
star
49

caravel_user_sram

Verilog
2
star
50

bwrap_devshell

Tarball a @numtide/devshell and bubblewrap it
Python
1
star
51

grapevine

Verilog
1
star
52

libparse-python

Python wrapper around Yosys's `libparse` module
C++
1
star
53

tinyfpga_rsa_demo

Coq
1
star
54

sky130_pa_ip__instramp

Instrumentation amplifier in sky130 by Phil Allen
1
star
55

EF_QSPI_XIP_CTRL

A QSPI XiP Flash Controller with a Direct Mapped Cache
Verilog
1
star
56

EF_eFPGA

Embedded FPGA IP
Verilog
1
star
57

EF_GPIO8

A generic 8-bit General Purpose I/O (GPIO) Peripheral
Verilog
1
star
58

tt-fpga-hdl-demo

TL-Verilog
1
star
59

silkflow-examples

Symbiflow Examples with a Silkflow flavor
Verilog
1
star
60

web_app_example

HTML
1
star
61

tinytapeout-rca

Verilog
1
star
62

open_pdk_techfiles

1
star
63

caravel_openlane

Dockerfile
1
star
64

silkflow

More straightforward utility for Symbiflow
Python
1
star
65

website_issues

1
star
66

clock-mesh-analysis

Verilog
1
star
67

utilities

A repo for various EDA related utilities
Python
1
star
68

drc-magic

Python
1
star
69

litex_ibex

Verilog
1
star
70

openram_tc_1kb

1
star
71

caravel_fasoc

Verilog
1
star
72

caravel-sim-infrastructure

HTML
1
star
73

tt-fpga-demo

Tcl
1
star
74

lef_parser

[WIP] Antlr4-based parser for LEF files
Python
1
star
75

OL-DFFRAM

Pre-hardened DFFRAM macros using DFFRAM
Verilog
1
star
76

caravel_aes_example

A user project example for caravel that uses https://github.com/secworks/aes
Verilog
1
star