Efabless (@efabless)
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efabless

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  • Stars
    star
    1,933
  • Global Org. Rank 9,726 (Top 4 %)
  • Registered almost 12 years ago
  • Most used languages
    Verilog     50.0 %
    Python
         25.0 %
    C
         4.2 %
    Tcl     4.2 %
    TL-Verilog     2.8 %
    HTML
         2.8 %
    Dockerfile
         2.8 %
    C++
         1.4 %
    Coq     1.4 %
    SourcePawn     1.4 %
    Perl
         1.4 %
    Assembly
         1.4 %
    Nix
         1.4 %
  • Location 🇺🇸 United States
  • Country Total Rank 6,485
  • Country Ranking
    TL-Verilog     2
    Verilog     6
    SourcePawn     20
    Tcl     22
    Coq     182
    Nix
         314
    Assembly
         475
    Perl
         511
    Dockerfile
         2,180
    Python
         3,149
    C
         3,788

Top repositories

1

caravel

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
Verilog
255
star
2

raven-picorv32

Silicon-validated SoC implementation of the PicoSoc/PicoRV32
Verilog
254
star
3

openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture
Python
205
star
4

caravel_user_project

https://caravel-user-project.readthedocs.io
Verilog
165
star
5

caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Verilog
133
star
6

chipignite-resources

63
star
7

volare

Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
Python
63
star
8

foss-asic-tools

FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already installed and ready to use.
Tcl
59
star
9

clear

Verilog
57
star
10

cace

Circuit Automatic Characterization Engine
Python
45
star
11

caravel_user_project_analog

Verilog
42
star
12

sky130_sram_macros_old

SourcePawn
35
star
13

mpw_precheck

Python
34
star
14

chipcraft---mest-course

TL-Verilog
29
star
15

caravel_board

C
28
star
16

proton

Perl
28
star
17

caravel_mgmt_soc_litex

https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
Verilog
25
star
18

sky130_klayout_pdk

Skywaters 130nm Klayout PDK
Python
17
star
19

caravel-lite

Verilog
16
star
20

ipm

Open-source IPs Package Manager (IPM)
Python
14
star
21

raptor

Arm Cortex-M0 based Customizable SoC for IoT Applications
Assembly
12
star
22

raptor_soc_template

Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
Verilog
12
star
23

clear_old

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.
Verilog
10
star
24

ravenna

32-bit RISC-V microcontroller
C
9
star
25

caravel-gf180mcu

This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
Verilog
8
star
26

nix-eda

Nix derivations for EDA tools
Nix
6
star
27

EF_PSRAM_CTRL

A Quad I/O SPI Pseudo Static RAM (PSRAM) Controller
Verilog
6
star
28

openrcx-calibration

Verilog
5
star
29

timer-tutorial

Source files for the timer-tutorial
Tcl
4
star
30

BusWrap

Python
4
star
31

Caravel_on_FPGA

Verilog
4
star
32

openfpga-2

Verilog
3
star
33

EF_UART

Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
Verilog
3
star
34

arduino-greenpak-shield

Shield for the GreenPak SLG468X chipset
Python
3
star
35

caravel_mini

Multi-Project Support for Caravel
Verilog
3
star
36

EF_TCC32

A 32-bit Timer/Counter/Capture Soft IP (Verilog)
Verilog
3
star
37

EF_LDOR1V8

Open Source, 3.3 V to 1.8 V, 100 mA Full Regulator
Python
3
star
38

openlane-ci-designs

Verilog
3
star
39

EF_SRAM_1024x32

Verilog
3
star
40

caravel_user_mini

Verilog
2
star
41

strive

Python
2
star
42

caravel_SI_testing

C
2
star
43

nm

Verilog
2
star
44

nldiff

Simple netlist comparison utility
Python
2
star
45

caravel_ibex

An example project that utilizes caravel user space for an ibex based SoC
Verilog
2
star
46

dockerized-verification-setup

This is a dockerized tool chain for running verilog DV customized for the sky130A-based projects.
Dockerfile
2
star
47

sram_macro_16KB

Verilog
2
star
48

sak-deprecated

SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA
Python
2
star
49

EF_UVM

Python
2
star
50

caravel_user_sram

Verilog
2
star
51

bwrap_devshell

Tarball a @numtide/devshell and bubblewrap it
Python
1
star
52

grapevine

Verilog
1
star
53

libparse-python

Python wrapper around Yosys's `libparse` module
C++
1
star
54

tinyfpga_rsa_demo

Coq
1
star
55

sky130_pa_ip__instramp

Instrumentation amplifier in sky130 by Phil Allen
1
star
56

EF_QSPI_XIP_CTRL

A QSPI XiP Flash Controller with a Direct Mapped Cache
Verilog
1
star
57

EF_eFPGA

Embedded FPGA IP
Verilog
1
star
58

EF_GPIO8

A generic 8-bit General Purpose I/O (GPIO) Peripheral
Verilog
1
star
59

tt-fpga-hdl-demo

TL-Verilog
1
star
60

silkflow-examples

Symbiflow Examples with a Silkflow flavor
Verilog
1
star
61

web_app_example

HTML
1
star
62

tinytapeout-rca

Verilog
1
star
63

open_pdk_techfiles

1
star
64

caravel_openlane

Dockerfile
1
star
65

silkflow

More straightforward utility for Symbiflow
Python
1
star
66

website_issues

1
star
67

clock-mesh-analysis

Verilog
1
star
68

utilities

A repo for various EDA related utilities
Python
1
star
69

drc-magic

Python
1
star
70

litex_ibex

Verilog
1
star
71

openram_tc_1kb

1
star
72

caravel_fasoc

Verilog
1
star
73

caravel-sim-infrastructure

HTML
1
star
74

tt-fpga-demo

Tcl
1
star
75

lef_parser

[WIP] Antlr4-based parser for LEF files
Python
1
star
76

OL-DFFRAM

Pre-hardened DFFRAM macros using DFFRAM
Verilog
1
star
77

caravel_aes_example

A user project example for caravel that uses https://github.com/secworks/aes
Verilog
1
star