Efabless (@efabless)
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efabless

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  • Stars
    star
    1,735
  • Global Org. Rank 10,395 (Top 4 %)
  • Registered over 11 years ago
  • Most used languages
    Verilog     47.7 %
    Python
         26.2 %
    C
         4.6 %
    Tcl     4.6 %
    Dockerfile
         3.1 %
    HTML
         3.1 %
    TL-Verilog     3.1 %
    Assembly
         1.5 %
    SourcePawn     1.5 %
    C++
         1.5 %
    Perl
         1.5 %
    Coq     1.5 %
  • Location πŸ‡ΊπŸ‡Έ United States
  • Country Total Rank 6,485
  • Country Ranking
    TL-Verilog     2
    Verilog     6
    SourcePawn     20
    Tcl     22
    Coq     204
    Assembly
         457
    Perl
         525
    Dockerfile
         1,921
    C
         3,633
    Python
         3,883

Top repositories

1

caravel

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
Verilog
255
star
2

raven-picorv32

Silicon-validated SoC implementation of the PicoSoc/PicoRV32
Verilog
254
star
3

caravel_user_project

https://caravel-user-project.readthedocs.io
Verilog
165
star
4

openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture
Python
144
star
5

caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Verilog
135
star
6

chipignite-resources

63
star
7

foss-asic-tools

FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already installed and ready to use.
Tcl
59
star
8

volare

Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
Python
53
star
9

caravel_user_project_analog

Verilog
39
star
10

sky130_sram_macros_old

SourcePawn
36
star
11

mpw_precheck

Python
34
star
12

clear

Verilog
30
star
13

caravel_board

C
28
star
14

proton

Perl
27
star
15

cace

Circuit Automatic Characterization Engine
Python
27
star
16

caravel_mgmt_soc_litex

https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
Verilog
25
star
17

chipcraft---mest-course

TL-Verilog
23
star
18

caravel-lite

Verilog
16
star
19

raptor

Arm Cortex-M0 based Customizable SoC for IoT Applications
Assembly
13
star
20

sky130_klayout_pdk

Skywaters 130nm Klayout PDK
Python
13
star
21

raptor_soc_template

Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
Verilog
12
star
22

ravenna

32-bit RISC-V microcontroller
C
11
star
23

ipm

Open-source IPs Package Manager (IPM)
Python
10
star
24

clear_old

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.
Verilog
7
star
25

caravel-gf180mcu

This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
Verilog
7
star
26

openrcx-calibration

Verilog
5
star
27

EF_PSRAM_CTRL

A Quad I/O SPI Pseudo Static RAM (PSRAM) Controller
Verilog
5
star
28

timer-tutorial

Source files for the timer-tutorial
Tcl
3
star
29

caravel_ibex

An example project that utilizes caravel user space for an ibex based SoC
Verilog
3
star
30

openfpga-2

Verilog
3
star
31

EF_UART

Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
Verilog
3
star
32

EF_TCC32

A 32-bit Timer/Counter/Capture Soft IP (Verilog)
Verilog
3
star
33

EF_LDOR1V8

Open Source, 3.3 V to 1.8 V, 100 mA Full Regulator
Python
3
star
34

openlane-ci-designs

Verilog
3
star
35

Caravel_on_FPGA

Verilog
3
star
36

nldiff

Simple netlist comparison utility
Python
2
star
37

strive

Python
2
star
38

caravel_SI_testing

C
2
star
39

nm

Verilog
2
star
40

open_pdk_techfiles

2
star
41

dockerized-verification-setup

This is a dockerized tool chain for running verilog DV customized for the sky130A-based projects.
Dockerfile
2
star
42

caravel_openlane

Dockerfile
2
star
43

utilities

A repo for various EDA related utilities
Python
2
star
44

arduino-greenpak-shield

Shield for the GreenPak SLG468X chipset
Python
2
star
45

mpc

Multi-Project Support for Caravel
Verilog
2
star
46

sak-deprecated

SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA
Python
2
star
47

EF_UVM

Python
2
star
48

BusWrap

Python
2
star
49

grapevine

Verilog
1
star
50

libparse-python

Python wrapper around Yosys's `libparse` module
C++
1
star
51

tinyfpga_rsa_demo

Coq
1
star
52

EF_GPIO8

A generic 8-bit General Purpose I/O (GPIO) Peripheral
Verilog
1
star
53

silkflow-examples

Symbiflow Examples with a Silkflow flavor
Verilog
1
star
54

web_app_example

HTML
1
star
55

tinytapeout-rca

Verilog
1
star
56

silkflow

More straightforward utility for Symbiflow
Python
1
star
57

website_issues

1
star
58

clock-mesh-analysis

Verilog
1
star
59

drc-magic

Python
1
star
60

litex_ibex

Verilog
1
star
61

openram_tc_1kb

1
star
62

caravel_fasoc

Verilog
1
star
63

sram_macro_16KB

Verilog
1
star
64

caravel-sim-infrastructure

HTML
1
star
65

tt-fpga-demo

Tcl
1
star
66

tt-fpga-hdl-demo

TL-Verilog
1
star
67

lef_parser

[WIP] Antlr4-based parser for LEF files
Python
1
star
68

OL-DFFRAM

Pre-hardened DFFRAM macros using DFFRAM
Verilog
1
star
69

caravel_aes_example

A user project example for caravel that uses https://github.com/secworks/aes
Verilog
1
star