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caravel
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.raven-picorv32
Silicon-validated SoC implementation of the PicoSoc/PicoRV32openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecturecaravel_user_project
https://caravel-user-project.readthedocs.iocaravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.chipignite-resources
volare
Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKsfoss-asic-tools
FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already installed and ready to use.clear
cace
Circuit Automatic Characterization Enginecaravel_user_project_analog
sky130_sram_macros_old
mpw_precheck
chipcraft---mest-course
caravel_board
proton
caravel_mgmt_soc_litex
https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/sky130_klayout_pdk
Skywaters 130nm Klayout PDKcaravel-lite
ipm
Open-source IPs Package Manager (IPM)raptor
Arm Cortex-M0 based Customizable SoC for IoT Applicationsraptor_soc_template
Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.clear_old
CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.ravenna
32-bit RISC-V microcontrollercaravel-gf180mcu
This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.nix-eda
Nix derivations for EDA toolsEF_PSRAM_CTRL
A Quad I/O SPI Pseudo Static RAM (PSRAM) Controlleropenrcx-calibration
timer-tutorial
Source files for the timer-tutorialBusWrap
Caravel_on_FPGA
openfpga-2
EF_UART
Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IParduino-greenpak-shield
Shield for the GreenPak SLG468X chipsetcaravel_mini
Multi-Project Support for CaravelEF_TCC32
A 32-bit Timer/Counter/Capture Soft IP (Verilog)EF_LDOR1V8
Open Source, 3.3 V to 1.8 V, 100 mA Full Regulatoropenlane-ci-designs
EF_SRAM_1024x32
caravel_user_mini
strive
caravel_SI_testing
nm
nldiff
Simple netlist comparison utilitycaravel_ibex
An example project that utilizes caravel user space for an ibex based SoCdockerized-verification-setup
This is a dockerized tool chain for running verilog DV customized for the sky130A-based projects.sram_macro_16KB
sak-deprecated
SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDAEF_UVM
caravel_user_sram
bwrap_devshell
Tarball a @numtide/devshell and bubblewrap itgrapevine
libparse-python
Python wrapper around Yosys's `libparse` moduletinyfpga_rsa_demo
sky130_pa_ip__instramp
Instrumentation amplifier in sky130 by Phil AllenEF_QSPI_XIP_CTRL
A QSPI XiP Flash Controller with a Direct Mapped CacheEF_eFPGA
Embedded FPGA IPEF_GPIO8
A generic 8-bit General Purpose I/O (GPIO) Peripheraltt-fpga-hdl-demo
silkflow-examples
Symbiflow Examples with a Silkflow flavorweb_app_example
tinytapeout-rca
open_pdk_techfiles
caravel_openlane
silkflow
More straightforward utility for Symbiflowclock-mesh-analysis
utilities
A repo for various EDA related utilitiesdrc-magic
litex_ibex
openram_tc_1kb
caravel_fasoc
caravel-sim-infrastructure
tt-fpga-demo
lef_parser
[WIP] Antlr4-based parser for LEF filesOL-DFFRAM
Pre-hardened DFFRAM macros using DFFRAMcaravel_aes_example
A user project example for caravel that uses https://github.com/secworks/aesLove Open Source and this site? Check out how you can help us