efabless/clear_old efabless/clear_old

  • Stars
    star
    10
  • Rank 1,807,489 (Top 36 %)
  • Language Verilog
  • License
    Apache License 2.0
  • Created over 2 years ago
  • Updated over 2 years ago
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efabless/clear_old
github

efabless

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Repository Details

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.

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