Bfloat16-Floating-Point-Arithmetic-Unit

Design and implementation of a pipelined Bfloat16 Floating Point Arithmetic Unit using VHDL. This unit can perform addition, subtraction, multiplication, division and fused multiply-add/subtract operations. Bfloat16 is a 16-bit floating-point data type developed at Google and currently used in their Tensor Processing Units (TPU's). Thanks to its dynamic range, the Bfloat16 format can be useful for Machine Learning applications that work well with low-precision representations of data. This Bfloat16 unit will be used to add custom RISC-V floating-point instructions to a RISC-V processor that can potentially be used as a hardware accelerator for Machine Learning applications. This model will also be tested on and FPGA and possibly modified to achieve optimal performance. Work is still in progress.

ADXL345-Accelerometer-Application

Developed an AXI-Lite SPI Master IP Block in VHDL to interface with the Digilent ADXL345 Accelerometer through one of the Pmod connectors of a Zedboard - Xilinx Zynq-7000 SoC. To transfer a specific number of bytes between the SPI Master and Slave (Accelerometer) devices, I utilized the Programmable System (PS) fabric of the Xilinx Zynq device that includes a software-programmable processor. Developed using the C programming language the corresponding driver functions and an application program that implements a digital level, a tool that would return the angle of incline of the Zedboard.

RISC-V-Single-Cycle-Processor

Design and implementation of a RISC-V Single-Cycle processor based on the RV32I base instruction set. Modeling of the RV32I building blocks was done using VHDL. RISC-V assembly and code generation tools were used to load a set of 32-bit RISC-V instructions into instruction memory and execute these instructions on the processor.