• Stars
    star
    72
  • Rank 438,337 (Top 9 %)
  • Language
    Scala
  • License
    Apache License 2.0
  • Created over 5 years ago
  • Updated over 2 years ago

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Repository Details

More Repositories

1

freedom

Source files for SiFive's Freedom platforms
Scala
1,058
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2

freedom-e-sdk

Open Source Software for Developing on the Freedom E Platform
C
567
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3

freedom-u-sdk

Freedom U Software Development Kit (FUSDK)
BitBake
275
star
4

freedom-tools

Tools for SiFive's Freedom Platform
Makefile
197
star
5

Kami

Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bluespec. It is actually a complete rewrite of an older version from MIT
Coq
188
star
6

sifive-blocks

Common RTL blocks used in SiFive's projects
Scala
179
star
7

freedom-metal

Bare Metal Compatibility Library for the Freedom Platform
C
153
star
8

fpga-shells

Scala
126
star
9

wake

The SiFive wake build tool
C++
86
star
10

elf2hex

Converts ELF files to HEX files that are suitable for Verilog's readmemh.
Shell
81
star
11

freedom-u540-c000-bootloader

Freedom U540-C000 Bootloader Code
C
77
star
12

benchmark-dhrystone

"DHRYSTONE" Benchmark Program by Reinhold P. Weicker
C
73
star
13

RiscvSpecFormal

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.
Haskell
73
star
14

duh

๐Ÿ‘พ Design โˆช Hardware
JavaScript
72
star
15

riscv-llvm

SiFive's LLVM working tree
C++
69
star
16

chisel-circt

Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
Scala
69
star
17

meta-sifive

SiFive OpenEmbedded / Yocto BSP Layer
BitBake
49
star
18

block-nvdla-sifive

Verilog
40
star
19

freedom-devicetree-tools

A linker script generator for SiFive's Freedom platform
C++
32
star
20

cinco

Port of Arduino environment for Freedom E 300 Dev Kit & HiFive Board
C++
31
star
21

last-week-in-risc-v

Weekly RISC-V Newsletter
Shell
28
star
22

ProcKami

Kami based processor implementations and specifications
Coq
24
star
23

pydevicetree

Python Library for Parsing Devicetree Source v1
Python
23
star
24

verilator

Fork of Verilator with prebuilt Ubuntu binaries (https://www.veripool.org/wiki/verilator)
C++
22
star
25

wit

Workspace Integration Tool
Python
22
star
26

riscv-vector-intrinsic-fuzzing

A random fuzz generator for the RISC-V vector extension intrinsics
C
17
star
27

freedom-studio

IDE for SiFive's Freedom Platform
16
star
28

FreeRTOS-metal

C
14
star
29

berkeley-hardfloat-chisel3

Hardfloat using chisel3
Scala
12
star
30

block-pio-sifive

An example of on-boarding a PIO block in with duh and wake
Scala
12
star
31

api-generator-sifive

Wake build descriptions of hardware generators
Python
12
star
32

soc-testsocket-sifive

A simple SoC for testing IP blocks
Scala
11
star
33

soc-freedom-sifive

e300 and u500 devkits
Scala
10
star
34

hifive1-revb-pendulum

An LED Ring and Accelerometer Pendulum Demo for HiFive1 Rev B
C
10
star
35

benchmark-mem-latency

simple cache latency test
C
9
star
36

devicetree-overlay-generator

Generates Devicetree overlays which encode the assumptions and/or sane defaults
Python
9
star
37

cmsis-svd-generator

Generates CMSIS-SVD xml files from DTS info and Register templates
Python
9
star
38

chisel-circt-demo

Demonstration of a project using sifive/chisel-circt
Scala
9
star
39

ldscript-generator

Freedom Metal Linker Script Generator
Python
8
star
40

Amazon-FreeRTOS

C
8
star
41

FpuKami

Coq
7
star
42

duh-scala

โ›๏ธ DUH component export to Scala
JavaScript
7
star
43

sifive-libc

Assembly
6
star
44

duh-ipxact

โŒ DUH IP-XACT import / export package
JavaScript
6
star
45

duh-schema

๐Ÿ“ DUH Schema
JavaScript
6
star
46

StdLibKami

Standard Library of Kami Modules
Coq
5
star
47

block-ark

๐ŸŒŠ๐Ÿ›ณ๏ธ๐Ÿ˜๐Ÿ˜๐Ÿ…๐Ÿˆ๐Ÿช๐Ÿซ๐Ÿ‘๐Ÿ๐Ÿ€๐Ÿ๐ŸŒ๐ŸŒ block with all sorts of bus interfaces
5
star
48

example-hpm

Demonstrates usage of the RISC-V hardware performance counter APIs.
C
5
star
49

scl-metal

C
5
star
50

duh-core

๐ŸŒฐ DUH core
JavaScript
4
star
51

debug-mechanism-comparison

Comparison of 2 proposed debug mechanisms.
HTML
4
star
52

example-pmp-baremetal

Example on how to program Physical Memory Protection Regions
C
4
star
53

example-cflush

An example demonstrating how to use cflush (CFLUSH.D.L1) and use FENCE to ensure flush complete
C
4
star
54

example-return-pass

A simple example for RTL run return pass
Makefile
3
star
55

xc3sprog

Imported from svn://svn.code.sf.net/p/xc3sprog/code/trunk
C++
3
star
56

soscl

SiFive Open Source Cryptographic Library
HTML
3
star
57

api-scala-sifive

Package for building Scala projects with wake
Python
3
star
58

example-pmp

C
3
star
59

freedom-gcc-metal

Bare Metal GCC for SiFive's Freedom Platform
Makefile
3
star
60

example-gpio

C
3
star
61

duhportinf

๐Ÿ‰ DUH port inference package
Python
3
star
62

freedom-qemu

QEMU System Emulator for SiFive's Freedom Platform
C
3
star
63

example-return-fail

A simple example for RTL run return fail
Makefile
3
star
64

freedom-elf2hex

Converts ELF files to HEX files that are suitable for Verilog's readmemh.
C
3
star
65

upf

upf tools
JavaScript
3
star
66

zephyr-sifive-freedom-template

Board template for building Zephyr RTOS for SiFive Freedom E-Series products
C
2
star
67

example-buserror

Freedom Metal Example for the SiFive Bus Error Unit
C
2
star
68

openocdcfg-generator

OpenOCD Configuration Generator for Freedom Metal
Python
2
star
69

example-chisel-wake

Example For Wake to run a Chisel design and unit test.
Scala
2
star
70

freedom-metal-docs

HTML
2
star
71

example-freertos-blinky-systemview

C
2
star
72

plic-baremetal

Low level setup for PLIC interrupt controller
C
2
star
73

duh-verilog

๐Ÿ‡ปVerilog import / export package
JavaScript
2
star
74

example-l2pm

Example code to demonstrate usage of Sifive L2 performance monitor counters to capture L2 cache event logs.
C
2
star
75

Segger_SystemView-metal

C
2
star
76

example-user-mode

C
2
star
77

trace-decoder-tests

Tests for SiFive trace decoder
Assembly
2
star
78

rocket-chip-wake

Wake build description for rocket-chip
2
star
79

riscv-fsf-gdb

C
2
star
80

example-firrtl-wake

Example Chisel modules and Chisel -> Verilog Wake flow
Scala
2
star
81

environment-blockci-sifive

Docker image and Wake environment for hardware development
Dockerfile
2
star
82

example-freertos-blinky

Standard Blinky freertos example
C
1
star
83

chisel-bootcamp-india

This is a trimmed down version of chisel bootcamp targeted for Indian undergraduate students. The Exercises here are sourced from different public chisel materials
Scala
1
star
84

testenv-metal

Test environment for freedom-metal
C
1
star
85

test-wfi-multicore

C
1
star
86

duh-svd

DUH to SVD converter
JavaScript
1
star
87

example-multicore-hello

C
1
star
88

environment-example-sifive

An example environment package
1
star
89

duh-bus

๐ŸšŒ Bus definition DUH documents
JavaScript
1
star
90

spdk-multithread

C
1
star
91

prepare-riscv-toolchain-qemu

Shell
1
star
92

example-freertos-minimal

C
1
star
93

duh-mem

โ“‚๏ธ DUH memory package
JavaScript
1
star
94

soc-iofpga-sifive

An IOFPGA SoC
Scala
1
star
95

firesim-ci-image

CI Image with LLVM and RISC-V utilities
Shell
1
star
96

freedom-gdb-metal

Bare Metal GDB for SiFive's Freedom Platform
Makefile
1
star
97

example-clic-nested-interrupts

A simple example demonstrating how to use CLIC preemptive (level and priority) nested interrupts
C
1
star
98

example-l2pf

Example code to demonstrate usage of Sifive L2 hardware prefetcher.
C
1
star
99

tree-sitter-wake

Wake grammar for tree-sitter
JavaScript
1
star
100

example-gpio-testbench

Exercises a GPIO connected to an RTL Testbench
C
1
star