Documentation for the Freedom Metal library can be found here.
There are no reviews yet. Be the first to send feedback to the community and the maintainers!
Documentation for the Freedom Metal library can be found here.
freedom
Source files for SiFive's Freedom platformsfreedom-e-sdk
Open Source Software for Developing on the Freedom E Platformfreedom-u-sdk
Freedom U Software Development Kit (FUSDK)freedom-tools
Tools for SiFive's Freedom PlatformKami
Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bluespec. It is actually a complete rewrite of an older version from MITsifive-blocks
Common RTL blocks used in SiFive's projectsfpga-shells
wake
The SiFive wake build toolelf2hex
Converts ELF files to HEX files that are suitable for Verilog's readmemh.freedom-u540-c000-bootloader
Freedom U540-C000 Bootloader Codebenchmark-dhrystone
"DHRYSTONE" Benchmark Program by Reinhold P. WeickerRiscvSpecFormal
The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.duh
👾 Design ∪ Hardwareblock-inclusivecache-sifive
riscv-llvm
SiFive's LLVM working treechisel-circt
Library to compile Chisel circuits using LLVM/MLIR (CIRCT)meta-sifive
SiFive OpenEmbedded / Yocto BSP Layerblock-nvdla-sifive
freedom-devicetree-tools
A linker script generator for SiFive's Freedom platformcinco
Port of Arduino environment for Freedom E 300 Dev Kit & HiFive Boardlast-week-in-risc-v
Weekly RISC-V NewsletterProcKami
Kami based processor implementations and specificationspydevicetree
Python Library for Parsing Devicetree Source v1verilator
Fork of Verilator with prebuilt Ubuntu binaries (https://www.veripool.org/wiki/verilator)wit
Workspace Integration Toolriscv-vector-intrinsic-fuzzing
A random fuzz generator for the RISC-V vector extension intrinsicsfreedom-studio
IDE for SiFive's Freedom PlatformFreeRTOS-metal
berkeley-hardfloat-chisel3
Hardfloat using chisel3block-pio-sifive
An example of on-boarding a PIO block in with duh and wakeapi-generator-sifive
Wake build descriptions of hardware generatorssoc-testsocket-sifive
A simple SoC for testing IP blockssoc-freedom-sifive
e300 and u500 devkitshifive1-revb-pendulum
An LED Ring and Accelerometer Pendulum Demo for HiFive1 Rev Bbenchmark-mem-latency
simple cache latency testdevicetree-overlay-generator
Generates Devicetree overlays which encode the assumptions and/or sane defaultscmsis-svd-generator
Generates CMSIS-SVD xml files from DTS info and Register templateschisel-circt-demo
Demonstration of a project using sifive/chisel-circtldscript-generator
Freedom Metal Linker Script GeneratorAmazon-FreeRTOS
FpuKami
duh-scala
⛏️ DUH component export to Scalasifive-libc
duh-ipxact
❌ DUH IP-XACT import / export packageduh-schema
📝 DUH SchemaStdLibKami
Standard Library of Kami Modulesblock-ark
🌊🛳️🐘🐘🐅🐈🐪🐫🐑🐏🐀🐁🐌🐌 block with all sorts of bus interfacesexample-hpm
Demonstrates usage of the RISC-V hardware performance counter APIs.scl-metal
duh-core
🌰 DUH coredebug-mechanism-comparison
Comparison of 2 proposed debug mechanisms.example-pmp-baremetal
Example on how to program Physical Memory Protection Regionsexample-cflush
An example demonstrating how to use cflush (CFLUSH.D.L1) and use FENCE to ensure flush completeexample-return-pass
A simple example for RTL run return passxc3sprog
Imported from svn://svn.code.sf.net/p/xc3sprog/code/trunksoscl
SiFive Open Source Cryptographic Libraryapi-scala-sifive
Package for building Scala projects with wakeexample-pmp
freedom-gcc-metal
Bare Metal GCC for SiFive's Freedom Platformexample-gpio
duhportinf
🐉 DUH port inference packagefreedom-qemu
QEMU System Emulator for SiFive's Freedom Platformexample-return-fail
A simple example for RTL run return failfreedom-elf2hex
Converts ELF files to HEX files that are suitable for Verilog's readmemh.upf
upf toolszephyr-sifive-freedom-template
Board template for building Zephyr RTOS for SiFive Freedom E-Series productsexample-buserror
Freedom Metal Example for the SiFive Bus Error Unitopenocdcfg-generator
OpenOCD Configuration Generator for Freedom Metalexample-chisel-wake
Example For Wake to run a Chisel design and unit test.freedom-metal-docs
example-freertos-blinky-systemview
plic-baremetal
Low level setup for PLIC interrupt controllerduh-verilog
🇻Verilog import / export packageexample-l2pm
Example code to demonstrate usage of Sifive L2 performance monitor counters to capture L2 cache event logs.Segger_SystemView-metal
example-user-mode
trace-decoder-tests
Tests for SiFive trace decoderrocket-chip-wake
Wake build description for rocket-chipriscv-fsf-gdb
example-firrtl-wake
Example Chisel modules and Chisel -> Verilog Wake flowenvironment-blockci-sifive
Docker image and Wake environment for hardware developmentexample-freertos-blinky
Standard Blinky freertos examplechisel-bootcamp-india
This is a trimmed down version of chisel bootcamp targeted for Indian undergraduate students. The Exercises here are sourced from different public chisel materialstestenv-metal
Test environment for freedom-metaltest-wfi-multicore
duh-svd
DUH to SVD converterexample-multicore-hello
environment-example-sifive
An example environment packageduh-bus
🚌 Bus definition DUH documentsspdk-multithread
prepare-riscv-toolchain-qemu
example-freertos-minimal
duh-mem
Ⓜ️ DUH memory packagesoc-iofpga-sifive
An IOFPGA SoCfiresim-ci-image
CI Image with LLVM and RISC-V utilitiesfreedom-gdb-metal
Bare Metal GDB for SiFive's Freedom Platformexample-clic-nested-interrupts
A simple example demonstrating how to use CLIC preemptive (level and priority) nested interruptsexample-l2pf
Example code to demonstrate usage of Sifive L2 hardware prefetcher.tree-sitter-wake
Wake grammar for tree-sitterexample-gpio-testbench
Exercises a GPIO connected to an RTL TestbenchLove Open Source and this site? Check out how you can help us