• Stars
    star
    24
  • Rank 986,245 (Top 20 %)
  • Language Coq
  • License
    Apache License 2.0
  • Created over 6 years ago
  • Updated almost 2 years ago

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Repository Details

Kami based processor implementations and specifications

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RiscvSpecFormal

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pydevicetree

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riscv-vector-intrinsic-fuzzing

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example-hpm

Demonstrates usage of the RISC-V hardware performance counter APIs.
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example-pmp-baremetal

Example on how to program Physical Memory Protection Regions
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example-cflush

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example-return-pass

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xc3sprog

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soscl

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api-scala-sifive

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example-pmp

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freedom-gcc-metal

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example-gpio

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freedom-qemu

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example-return-fail

A simple example for RTL run return fail
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Converts ELF files to HEX files that are suitable for Verilog's readmemh.
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example-l2pm

Example code to demonstrate usage of Sifive L2 performance monitor counters to capture L2 cache event logs.
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example-user-mode

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trace-decoder-tests

Tests for SiFive trace decoder
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rocket-chip-wake

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riscv-fsf-gdb

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example-firrtl-wake

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example-freertos-blinky

Standard Blinky freertos example
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testenv-metal

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test-wfi-multicore

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example-multicore-hello

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environment-example-sifive

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spdk-multithread

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prepare-riscv-toolchain-qemu

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example-freertos-minimal

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duh-mem

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soc-iofpga-sifive

An IOFPGA SoC
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CI Image with LLVM and RISC-V utilities
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freedom-gdb-metal

Bare Metal GDB for SiFive's Freedom Platform
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example-clic-nested-interrupts

A simple example demonstrating how to use CLIC preemptive (level and priority) nested interrupts
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example-l2pf

Example code to demonstrate usage of Sifive L2 hardware prefetcher.
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tree-sitter-wake

Wake grammar for tree-sitter
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example-gpio-testbench

Exercises a GPIO connected to an RTL Testbench
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