Discover sifive/environment-blockci-sifive Open Source project

Open Source Software for Developing on the Freedom E Platform

1,058

freedom-e-sdk

567

freedom-u-sdk

Freedom U Software Development Kit (FUSDK)

BitBake

275

freedom-tools

Tools for SiFive's Freedom Platform

Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bluespec. It is actually a complete rewrite of an older version from MIT

197

Kami

Common RTL blocks used in SiFive's projects

188

sifive-blocks

Bare Metal Compatibility Library for the Freedom Platform

179

freedom-metal

153

fpga-shells

The SiFive wake build tool

126

wake

Converts ELF files to HEX files that are suitable for Verilog's readmemh.

elf2hex

Freedom U540-C000 Bootloader Code

freedom-u540-c000-bootloader

benchmark-dhrystone

"DHRYSTONE" Benchmark Program by Reinhold P. Weicker

RiscvSpecFormal

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

Haskell

duh

👾 Design ∪ Hardware

block-inclusivecache-sifive

SiFive's LLVM working tree

riscv-llvm

Library to compile Chisel circuits using LLVM/MLIR (CIRCT)

chisel-circt

SiFive OpenEmbedded / Yocto BSP Layer

meta-sifive

BitBake

block-nvdla-sifive

Verilog

freedom-devicetree-tools

A linker script generator for SiFive's Freedom platform

Port of Arduino environment for Freedom E 300 Dev Kit & HiFive Board

cinco

last-week-in-risc-v

Weekly RISC-V Newsletter

Kami based processor implementations and specifications

ProcKami

Python Library for Parsing Devicetree Source v1

pydevicetree

Fork of Verilator with prebuilt Ubuntu binaries (https://www.veripool.org/wiki/verilator)

verilator

Workspace Integration Tool

wit

A random fuzz generator for the RISC-V vector extension intrinsics

riscv-vector-intrinsic-fuzzing

freedom-studio

IDE for SiFive's Freedom Platform

FreeRTOS-metal

berkeley-hardfloat-chisel3

Hardfloat using chisel3

An example of on-boarding a PIO block in with duh and wake

block-pio-sifive

Wake build descriptions of hardware generators

api-generator-sifive

A simple SoC for testing IP blocks

soc-testsocket-sifive

soc-freedom-sifive

e300 and u500 devkits

An LED Ring and Accelerometer Pendulum Demo for HiFive1 Rev B

hifive1-revb-pendulum

benchmark-mem-latency

simple cache latency test

devicetree-overlay-generator

Generates Devicetree overlays which encode the assumptions and/or sane defaults

Generates CMSIS-SVD xml files from DTS info and Register templates

cmsis-svd-generator

Demonstration of a project using sifive/chisel-circt

chisel-circt-demo

Freedom Metal Linker Script Generator

ldscript-generator

Amazon-FreeRTOS

FpuKami

⛏️ DUH component export to Scala

duh-scala

❌ DUH IP-XACT import / export package

sifive-libc

Assembly

duh-ipxact

duh-schema

📝 DUH Schema

Standard Library of Kami Modules

StdLibKami

🌊🛳️🐘🐘🐅🐈🐪🐫🐑🐏🐀🐁🐌🐌 block with all sorts of bus interfaces

block-ark

example-hpm

Demonstrates usage of the RISC-V hardware performance counter APIs.

scl-metal

duh-core

🌰 DUH core

Comparison of 2 proposed debug mechanisms.

debug-mechanism-comparison

HTML

example-pmp-baremetal

Example on how to program Physical Memory Protection Regions

example-cflush

An example demonstrating how to use cflush (CFLUSH.D.L1) and use FENCE to ensure flush complete

example-return-pass

A simple example for RTL run return pass

Imported from svn://svn.code.sf.net/p/xc3sprog/code/trunk

xc3sprog

SiFive Open Source Cryptographic Library

soscl

HTML

api-scala-sifive

Package for building Scala projects with wake

Bare Metal GCC for SiFive's Freedom Platform

example-pmp

freedom-gcc-metal

🐉 DUH port inference package

example-gpio

duhportinf

QEMU System Emulator for SiFive's Freedom Platform

freedom-qemu

example-return-fail

A simple example for RTL run return fail

Converts ELF files to HEX files that are suitable for Verilog's readmemh.

freedom-elf2hex

upf

upf tools

Board template for building Zephyr RTOS for SiFive Freedom E-Series products

zephyr-sifive-freedom-template

example-buserror

Freedom Metal Example for the SiFive Bus Error Unit

openocdcfg-generator

OpenOCD Configuration Generator for Freedom Metal

Example For Wake to run a Chisel design and unit test.

example-chisel-wake

Low level setup for PLIC interrupt controller

freedom-metal-docs

HTML

example-freertos-blinky-systemview

plic-baremetal

duh-verilog

🇻Verilog import / export package

Example code to demonstrate usage of Sifive L2 performance monitor counters to capture L2 cache event logs.

example-l2pm

Segger_SystemView-metal

example-user-mode

trace-decoder-tests

Tests for SiFive trace decoder

Assembly

rocket-chip-wake

Wake build description for rocket-chip

riscv-fsf-gdb

example-firrtl-wake

Example Chisel modules and Chisel -> Verilog Wake flow

Standard Blinky freertos example

example-freertos-blinky

chisel-bootcamp-india

This is a trimmed down version of chisel bootcamp targeted for Indian undergraduate students. The Exercises here are sourced from different public chisel materials

Test environment for freedom-metal

testenv-metal

test-wfi-multicore

duh-svd

DUH to SVD converter

An example environment package

example-multicore-hello

environment-example-sifive

duh-bus

🚌 Bus definition DUH documents

spdk-multithread

prepare-riscv-toolchain-qemu

example-freertos-minimal

duh-mem

Ⓜ️ DUH memory package

soc-iofpga-sifive

An IOFPGA SoC

CI Image with LLVM and RISC-V utilities

firesim-ci-image

Bare Metal GDB for SiFive's Freedom Platform

freedom-gdb-metal

A simple example demonstrating how to use CLIC preemptive (level and priority) nested interrupts

example-clic-nested-interrupts

example-l2pf

Example code to demonstrate usage of Sifive L2 hardware prefetcher.

tree-sitter-wake

Wake grammar for tree-sitter