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@lowRISC

lowRISC

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14.3 %

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6.1 %

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6.1 %

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4.1 %

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4.1 %

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opentitan

OpenTitan: Open source silicon root of trust

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

lowrisc-chip

The root repo for lowRISC project and FPGA demos.

style-guides

lowRISC Style Guides

riscv-llvm

RISC-V support for LLVM projects (LLVM, Clang, ...)

muntjac

64-bit multicore RISC-V processor

lowrisc-fpga

Untethered (stand-alone) FPGA implementation of the lowRISC SoC

ibex-demo-system

A demo system for Ibex including debug support and some peripherals

hjson_to_gantt

A Python script to generate a Gantt chart from a (H)JSON input

lowrisc-toolchains

UNSUPPORTED INTERNAL toolchain builds

ot-sca

Side-channel analysis setup for OpenTitan

Jupyter Notebook

rocket

sonata-system

A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI

lowrisc-nexys4

FPGA demo for Digilent NEXYS 4 board

manticore

riscv-compliance

TEMPORARY FORK of the riscv-compliance repository

ariane-ethernet

open-source Ethenet media access controller for Ariane on Genesys-2

lowrisc.github.io

Generated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-site

uncore

epic-c-example

ePIC (Embedded PIC) example: kernel and relocatable loadable app

abicop

Work towards a "golden model" of the RISC-V calling convention(s)

synfi

OpenTitan FI formal verification framework

fpga-zynq

lowrisc-site

ibex-demo-system-labs

Labs for the Ibex Demo System

lowrisc-docker

Docker files to generate development environment for multiple releases.

longfruit

symphony-system

An integration of CHERIoT Ibex with OpenTitan Earl Grey, part of the Sunburst project funded by UKRI

rv_plic

Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC). DEPRECATED in favour of the OpenTitan PLIC: https://github.com/lowRISC/opentitan/tree/master/hw/ip/rv_plic

socip

Collection of IP cores usable to lowRISC SoC

container-hotplug

Hot-plug devices into a Docker container as they are plugged.

gsoc-sim-mem

A simulated memory controller for use in FPGA designs that want to model real system performance

minion_subsystem

minion_subsystem for lowrisc rocket core (version 2)

sonata-software

Software, build flows and examples for the Sonata System

lowrisc-web

lowrisc.org web site sources

crt

Compiler Repository Toolkit

lowrisc-quickstart

Minimised environment for bandwidth limited sites

junctions

A repository for peripheral components and IO devices associated with the RocketChip project

lowrisc-nexys4-video

lowrisc-kc705

KC705 implementation of the lowRISC unthethered SoC

lowrisc-nix

lowRISC Nix Packages and Environments

bazel-release

Bazel automated GitHub release process

riscv-llvm-integration

Temporary downstream RISC-V LLVM tree. You almost certainly want upstream LLVM instead (see https://llvm.org/docs/GettingStarted.html)

mundane

Mirror of: https://fuchsia.googlesource.com/mundane/

lowrisc-vcu108

lowrisc-artya7

Port of lowrisc to low cost artya7-100 FPGA

riscv-elf-psabi-sanity-checker

High-level C Compiler Sanity Checks for RISC-V ELF psABI

lowrisc-tag-tests

misc-linters

Some Internal Linter Scripts

lowrisc-doc

A repo to store all document files other than the website itself.