@lowRISC
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lowRISC

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  • Stars
    star
    5,734
  • Global Org. Rank 4,048 (Top 2 %)
  • Registered over 10 years ago
  • Most used languages
    SystemVerilog     22.4 %
    Python
         14.3 %
    C
         14.3 %
    Scala
         6.1 %
    Rust
         6.1 %
    Shell
         6.1 %
    Makefile     6.1 %
    HTML
         4.1 %
    C++
         4.1 %
    Tcl     4.1 %
    Nix
         2.0 %
    Dockerfile
         2.0 %
    Verilog     2.0 %
    Jupyter Notebook
         2.0 %
    CSS
         2.0 %
    Starlark     2.0 %

Top repositories

1

opentitan

OpenTitan: Open source silicon root of trust
SystemVerilog
2,485
star
2

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
SystemVerilog
1,327
star
3

lowrisc-chip

The root repo for lowRISC project and FPGA demos.
SystemVerilog
593
star
4

style-guides

lowRISC Style Guides
354
star
5

riscv-llvm

RISC-V support for LLVM projects (LLVM, Clang, ...)
Shell
246
star
6

muntjac

64-bit multicore RISC-V processor
SystemVerilog
73
star
7

lowrisc-fpga

Untethered (stand-alone) FPGA implementation of the lowRISC SoC
C
54
star
8

ibex-demo-system

A demo system for Ibex including debug support and some peripherals
C
46
star
9

hjson_to_gantt

A Python script to generate a Gantt chart from a (H)JSON input
Python
31
star
10

lowrisc-toolchains

UNSUPPORTED INTERNAL toolchain builds
Shell
30
star
11

ot-sca

Side-channel analysis setup for OpenTitan
Jupyter Notebook
27
star
12

rocket

Scala
27
star
13

sonata-system

A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
SystemVerilog
24
star
14

lowrisc-nexys4

FPGA demo for Digilent NEXYS 4 board
Tcl
22
star
15

manticore

Rust
16
star
16

riscv-compliance

TEMPORARY FORK of the riscv-compliance repository
C
15
star
17

ariane-ethernet

open-source Ethenet media access controller for Ariane on Genesys-2
SystemVerilog
15
star
18

lowrisc.github.io

Generated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-site
HTML
12
star
19

uncore

Scala
10
star
20

epic-c-example

ePIC (Embedded PIC) example: kernel and relocatable loadable app
C
10
star
21

abicop

Work towards a "golden model" of the RISC-V calling convention(s)
Python
10
star
22

synfi

OpenTitan FI formal verification framework
Python
9
star
23

fpga-zynq

Verilog
9
star
24

lowrisc-site

CSS
9
star
25

ibex-demo-system-labs

Labs for the Ibex Demo System
C
8
star
26

lowrisc-docker

Docker files to generate development environment for multiple releases.
Dockerfile
8
star
27

longfruit

Python
7
star
28

symphony-system

An integration of CHERIoT Ibex with OpenTitan Earl Grey, part of the Sunburst project funded by UKRI
Python
7
star
29

rv_plic

Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC). DEPRECATED in favour of the OpenTitan PLIC: https://github.com/lowRISC/opentitan/tree/master/hw/ip/rv_plic
SystemVerilog
7
star
30

socip

Collection of IP cores usable to lowRISC SoC
SystemVerilog
5
star
31

container-hotplug

Hot-plug devices into a Docker container as they are plugged.
Rust
5
star
32

gsoc-sim-mem

A simulated memory controller for use in FPGA designs that want to model real system performance
SystemVerilog
4
star
33

minion_subsystem

minion_subsystem for lowrisc rocket core (version 2)
SystemVerilog
4
star
34

sonata-software

Software, build flows and examples for the Sonata System
Python
4
star
35

lowrisc-web

lowrisc.org web site sources
HTML
3
star
36

crt

Compiler Repository Toolkit
Starlark
3
star
37

lowrisc-quickstart

Minimised environment for bandwidth limited sites
Makefile
3
star
38

junctions

A repository for peripheral components and IO devices associated with the RocketChip project
Scala
3
star
39

lowrisc-nexys4-video

Tcl
2
star
40

lowrisc-kc705

KC705 implementation of the lowRISC unthethered SoC
C
2
star
41

lowrisc-nix

lowRISC Nix Packages and Environments
Nix
2
star
42

bazel-release

Bazel automated GitHub release process
Shell
1
star
43

riscv-llvm-integration

Temporary downstream RISC-V LLVM tree. You almost certainly want upstream LLVM instead (see https://llvm.org/docs/GettingStarted.html)
C++
1
star
44

mundane

Mirror of: https://fuchsia.googlesource.com/mundane/
Rust
1
star
45

lowrisc-vcu108

SystemVerilog
1
star
46

lowrisc-artya7

Port of lowrisc to low cost artya7-100 FPGA
Makefile
1
star
47

riscv-elf-psabi-sanity-checker

High-level C Compiler Sanity Checks for RISC-V ELF psABI
C
1
star
48

lowrisc-tag-tests

C++
1
star
49

misc-linters

Some Internal Linter Scripts
Python
1
star
50

lowrisc-doc

A repo to store all document files other than the website itself.
Makefile
1
star