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opentitan
OpenTitan: Open source silicon root of trustibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.lowrisc-chip
The root repo for lowRISC project and FPGA demos.style-guides
lowRISC Style Guidesriscv-llvm
RISC-V support for LLVM projects (LLVM, Clang, ...)muntjac
64-bit multicore RISC-V processorlowrisc-fpga
Untethered (stand-alone) FPGA implementation of the lowRISC SoCibex-demo-system
A demo system for Ibex including debug support and some peripheralshjson_to_gantt
A Python script to generate a Gantt chart from a (H)JSON inputlowrisc-toolchains
UNSUPPORTED INTERNAL toolchain buildsot-sca
Side-channel analysis setup for OpenTitanrocket
sonata-system
A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRIlowrisc-nexys4
FPGA demo for Digilent NEXYS 4 boardmanticore
riscv-compliance
TEMPORARY FORK of the riscv-compliance repositoryariane-ethernet
open-source Ethenet media access controller for Ariane on Genesys-2lowrisc.github.io
Generated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-siteuncore
epic-c-example
ePIC (Embedded PIC) example: kernel and relocatable loadable appabicop
Work towards a "golden model" of the RISC-V calling convention(s)synfi
OpenTitan FI formal verification frameworkfpga-zynq
lowrisc-site
ibex-demo-system-labs
Labs for the Ibex Demo Systemlowrisc-docker
Docker files to generate development environment for multiple releases.longfruit
symphony-system
An integration of CHERIoT Ibex with OpenTitan Earl Grey, part of the Sunburst project funded by UKRIrv_plic
Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC). DEPRECATED in favour of the OpenTitan PLIC: https://github.com/lowRISC/opentitan/tree/master/hw/ip/rv_plicsocip
Collection of IP cores usable to lowRISC SoCcontainer-hotplug
Hot-plug devices into a Docker container as they are plugged.gsoc-sim-mem
A simulated memory controller for use in FPGA designs that want to model real system performanceminion_subsystem
minion_subsystem for lowrisc rocket core (version 2)sonata-software
Software, build flows and examples for the Sonata Systemlowrisc-web
lowrisc.org web site sourcescrt
Compiler Repository Toolkitlowrisc-quickstart
Minimised environment for bandwidth limited sitesjunctions
A repository for peripheral components and IO devices associated with the RocketChip projectlowrisc-nexys4-video
lowrisc-kc705
KC705 implementation of the lowRISC unthethered SoClowrisc-nix
lowRISC Nix Packages and Environmentsbazel-release
Bazel automated GitHub release processriscv-llvm-integration
Temporary downstream RISC-V LLVM tree. You almost certainly want upstream LLVM instead (see https://llvm.org/docs/GettingStarted.html)lowrisc-vcu108
lowrisc-artya7
Port of lowrisc to low cost artya7-100 FPGAriscv-elf-psabi-sanity-checker
High-level C Compiler Sanity Checks for RISC-V ELF psABIlowrisc-tag-tests
misc-linters
Some Internal Linter Scriptslowrisc-doc
A repo to store all document files other than the website itself.Love Open Source and this site? Check out how you can help us