There are no reviews yet. Be the first to send feedback to the community and the maintainers!
aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.sha256
Hardware implementation of the SHA-256 cryptographic hash functiontrng
True Random Number Generator core implemented in Verilog.sha1
Verilog implementation of the SHA-1 cryptgraphic hash functionchacha
Verilog 2001 implementation of the ChaCha stream cipher.sha512
Verilog implementation of the SHA-512 hash function.blake2
Hardware implementation of the blake2 hash functionblake2s
Verilog implementation of the 32-bit version of the Blake2 hash functionsha3
FIPS 202 compliant SHA-3 core in Verilogmodexp
Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.siphash
Hardware implementation of the SipHash short-inout PRFcmac
Implementation of the CMAC keyed hash function using AES as block cipher.chacha_testvectors
Generator and Internet Draft (I-D) documenting test vectors for the stream cipher ChaCha.uart
A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.ChaCha20-Poly1305
Hardware implementation of the ChaCha20-Poly1305 AEAD constructiongift
Hardware implementation of the GIFT-128 lightweight block cipherpoly1305
Hardware implementation of the poly1305 message authentication function.rosc_entropy
Entropy source based on jitter between multiple, digital ring oscillators.6502
Verilog implementation of a MOS6502 compatible CPU core.prince
The Prince lightweight block cipher in Verilog.ed25519
ed25519 public key signature implemented in Verilog.md5
Hardware implementation of the hash function md5figaro
Implementation of the FiGaRO TRNG for FPGAscbc
CBC block cipher mode of operation for AES.verilator_template
(Hopefully) simple template for a Verilator SystemVerilog project with a usable testbenchascon
Verilog implementation of the ASCON lightweight authenticated encryption and hashing algorithmgcm
Galois Couter Mode implementation in Verilog.rc4
An experimental RC4 hardware implementation with one cycle/iteration performance.aes_6502
My attempt at making a fast AES-128 implementation on MOS 6502aes_mask
Experimental core for performing masking of AES by generating noise.curve25519
Verilog 2001 of the Curve25519 elliptic curve based function.hmac
HMAC-SHA-256 in Verilog 2001xtea
Verilog implementation of the xtea block cipheravalanche_entropy
Entropy collector and provider for an external avalanche noise based entropy source.grain128
Hardware implementation of the Grain128AEAD stream cipherccm
ccm mode hardware implementationview_rnd
A simple program for viewing random values as an image.vga
vgatracegen
A tool for generating synthetic traces with side-channel leakage.hc
Hardware implementation of the HC stream cipher.salsa20
Sals20 Stream Cipher core in Verilogr5
A simple Verilog implementation of RISC-V.extract_ev_data
Pure Python program used to extract EV data from Mozilla CA roots. Used to generate EV validation data in sslyze.fpga_eth_filter
FPGA based Ethernet traffic filter and manipulator for the TerasIC ETHERNET-HSMC Cardbigmath
Project for testing and developing HW-implementations of integer operations. mult, mod, add, div etc.chaskey
Verilog implementation of the Chaskey lightweight message authentication code (MAC) function.online_tester
Online tester/monitor of random number generators. Based om AIS31 but modular.blake3
Hardware implementation of the Blake3 hash functionsnow5
Hardware implementation of the SNOW-V stream cipher.aead_aes_siv_cmac
Hardware implementation of the AEAD_AES_SIV_CMACrandom_tools
A collection of tools used to analyze random number data files, extract entropy etc.tang_nano_rng
Implementation of a high quality random number generator on the Tang Nano FPGA boardcoretest
Test structure for cores developed as part of the Cryptech Open HSM projectsiphash_6502
Implementation of the SipHash keyed hash function in MOS 6502 assemblerTweetnacl
Python implementation of the TweetNaCl cryptograhic librarypyat88ck590
Python program to talk to the Atmel AT88CK590 Crypto Authentication Evaulation Kit.stanford_cryptography1
Solutions to programming problems and assignments in the Cryptography 1 coursekeywrap
RFC 3394 keywrap cipher mode implemented in Verilog 2001.ubbefpga
Very simple HW design to test FPGA development using the Terasic DE0-Nano boardblabla
Implementation of the BlaBla version of the ChaCha stream ciphervndecorrelator
A Verilog implementation of a von Neumann decorrelatorrobber_language
Hardware implementation of a decoder/encoder for the Robber languageca_prng
Cellular Automata based PRNGmkmif
interface to external master key memory.fpga_entropy
Test implementation of FPGA-internal entropy source.coretest_bp_entropy
Coretest system for testing the FPGA based entropy source by Berndt Paysan.verilogtest
Repo for test of HW implementations written in Verilog.rc4_6502
MOS 6502 implementation of the old RC4 stream cipher. Yes, it is broken.advent_of_code_2019
Solutions to Adevent of Code 2019test_core
A very simple test core.huffman
Python implementation of Huffman encoding and decoding. Just for fun.coretest_test_core
The coretest module combined with the test_core as a test module.xchacha
Hardware implementation of the extended-nonce ChaCha stream cipherqarma
Verilog implementation of the lightweight block cipher QARMAocb
Verilog implementation of the OCB authenticated encryption mode.Love Open Source and this site? Check out how you can help us