secworks/sha256 secworks/sha256

  • Stars
    star
    316
  • Rank 132,587 (Top 3 %)
  • Language Verilog
  • License
    BSD 2-Clause "Sim...
  • Created almost 11 years ago
  • Updated 6 months ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
secworks/sha256
github

secworks

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Hardware implementation of the SHA-256 cryptographic hash function

build-openlane-sky130

sha256

Implementation status

The core has been completed for a long time and been used in several designs in ASICs as well as in FPGAs. The core is considered mature and ready for use. Minor changes are non-functional cleanups of code.

Introduction

Hardware implementation of the SHA-256 cryptographic hash function with support for both SHA-256 and SHA-224. The implementation is written in Verilog 2001 compliant code. The implementation includes the main core as well as wrappers that provides interfaces for simple integration.

This is a low area implementation that iterates over the rounds but there is no sharing of operations such as adders.

The hardware implementation is complemented by a functional model written in Python.

Note that the core does NOT implement padding of final block. The caller is expected to handle padding.

Implementation details

The sha256 design is divided into the following sections.

  • src/rtl - RTL source files
  • src/tb - Testbenches for the RTL files
  • src/model/python - Functional model written in python
  • doc - documentation (currently not done.)
  • toolruns - Where tools are supposed to be run. Includes a Makefile for building and simulating the design using Icarus Verilog. There are also targets for linting the core using Verilator.

The actual core consists of the following files:

  • sha256_core.v - The core itself with wide interfaces.
  • sha256_w_mem.v - W message block memory and block expansion logic.
  • sha256_k_constants.v - K constants ROM memory.

The top level entity is called sha256_core. This entity has wide interfaces (512 bit block input, 256 bit digest). In order to make it usable you probably want to wrap the core with a bus interface.

The provided top level wrapper, sha256.v provides a simple 32-bit memory like interface. The core (sha256_core) will sample all data inputs when given the init or next signal. the wrapper contains additional data registers. This allows you to load a new block while the core is processing the previous block.

The core supports both sha224 and sha256 modes. The default mode is sha256. The mode bit is located in the ADDR_CTRL API register and this means that when writing to this register to start processing a block, care must be taken to set the mode bit to the intended mode. This means that old code that for example simply wrote 0x01 to initiate SHA256 processing will now initiate SHA224 processing. Writing 0x05 will now initiate SHA256 processing.

Regarding SHA224, it is up to the user to only read seven, not eight words from the digest registers. The core will update the LSW too.

Streaming interface

There is a streaming interface for the core contributed by Olof Kindgren.

  • src/interfaces/stream/rtl - RTL source file for wrapped core
  • src/interfaces/stream/tb - Testbench for the wrapped core

AXI4 interface

NOTE This interface is currently being developed. Expect bugs as this interface is still under development.

There is now an AXI4 interface for the core contributed by Sanjay A Menon. The interface wraps sha256_core, replacing sha256.v

The interface provides an AXI4-Lite slave interface with added hash complete interrupt signal. Chip select is implemented via axi_awprot signal.

  • src/interfaces/axi4/rtl - RTL source file for wrapped core
  • src/interfaces/axi4/tb - Testbench for the wrapped core

FuseSoC Integration

This core is supported by the FuseSoC core package manager and build system. Some quick FuseSoC instructions:

install FuseSoC

pip install fusesoc

Create and enter a new workspace

mkdir workspace && cd workspace

Register sha256 as a library in the workspace

fusesoc library add sha256 /path/to/sha256

...if repo is available locally or... ...to get the upstream repo

fusesoc library add sha256 https://github.com/secworks/sha256

To run lint

fusesoc run --target=lint secworks:crypto:sha256

Run tb_sha256 testbench

fusesoc run --target=tb_sha256 secworks:crypto:sha256

Run with modelsim instead of default tool (icarus)

fusesoc run --target=tb_sha256 --tool=modelsim secworks:crypto:sha256

List all targets

fusesoc core show secworks:crypto:sha256

ASIC-results

Implementation in 40 nm low power standard cell process.

  • Area: 14200 um2
  • Combinational cells: 2344.9230
  • Non-combinational cells: 2902.4856
  • Clock frequency: 250 MHz

Fpga-results

Altera Cyclone FPGAs

Implementation results using Altera Quartus-II 13.1.

Cyclone IV E

  • EP4CE6F17C6
  • 3882 LEs
  • 1813 registers
  • 74 MHz
  • 66 cycles latency

Cyclone IV GX

  • EP4CGX22CF19C6
  • 3773 LEs
  • 1813 registers
  • 76 MHz
  • 66 cycles latency

Cyclone V

  • 5CGXFC7C7F23C8
  • 1469 ALMs
  • 1813 registers
  • 79 MHz
  • 66 cycles latency

Microchip

IGLOO2

  • Tool: Libero v 12.4
  • Device: M2GL090TS-1FG484I
  • LUTs: 2811
  • SLEs: 1900
  • BRAMs: 0
  • Fmax: 114 MHz

Xilinx FPGAs

Implementation results using ISE 14.7.

Spartan-6

  • xc6slx45-3csg324
  • 2012 LUTs
  • 688 Slices
  • 1929 regs
  • 70 MHz
  • 66 cycles latency

Artix-7

  • xc7a200t-3fbg484
  • 2471 LUTs
  • 747 Slices
  • 1930 regs
  • 108 MHz
  • 66 cycles latency

Implementation results using Vivado 2014.4.

Zynq-7030

  • xc7z030fbg676-1
  • 2308 LUTs
  • 796 Slices
  • 2116 regs
  • 116 MHz
  • 66 cycles latency

Implementation results using Vivado v.2019.2

Results kindly provided by Sanjay-A-Menon. Implemented design includes the AXI4 wrapper.

Zynq-7020

  • Device: 7z020clg400-1
  • Slice LUTs: 2555
  • Slice regs: 2606
  • Fmax: 78 MHz
  • 66 cycles latency

More Repositories

1

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
Verilog
334
star
2

trng

True Random Number Generator core implemented in Verilog.
Verilog
72
star
3

sha1

Verilog implementation of the SHA-1 cryptgraphic hash function
Verilog
51
star
4

chacha

Verilog 2001 implementation of the ChaCha stream cipher.
Verilog
38
star
5

sha512

Verilog implementation of the SHA-512 hash function.
Verilog
33
star
6

blake2

Hardware implementation of the blake2 hash function
Verilog
25
star
7

blake2s

Verilog implementation of the 32-bit version of the Blake2 hash function
Verilog
20
star
8

sha3

FIPS 202 compliant SHA-3 core in Verilog
Verilog
17
star
9

modexp

Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
Verilog
17
star
10

siphash

Hardware implementation of the SipHash short-inout PRF
Verilog
16
star
11

cmac

Implementation of the CMAC keyed hash function using AES as block cipher.
Verilog
12
star
12

chacha_testvectors

Generator and Internet Draft (I-D) documenting test vectors for the stream cipher ChaCha.
C
10
star
13

uart

A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.
Verilog
8
star
14

ChaCha20-Poly1305

Hardware implementation of the ChaCha20-Poly1305 AEAD construction
Verilog
8
star
15

gift

Hardware implementation of the GIFT-128 lightweight block cipher
Verilog
8
star
16

poly1305

Hardware implementation of the poly1305 message authentication function.
Verilog
8
star
17

rosc_entropy

Entropy source based on jitter between multiple, digital ring oscillators.
Verilog
7
star
18

6502

Verilog implementation of a MOS6502 compatible CPU core.
Verilog
7
star
19

prince

The Prince lightweight block cipher in Verilog.
Verilog
7
star
20

ed25519

ed25519 public key signature implemented in Verilog.
Verilog
7
star
21

md5

Hardware implementation of the hash function md5
Verilog
6
star
22

figaro

Implementation of the FiGaRO TRNG for FPGAs
Verilog
6
star
23

cbc

CBC block cipher mode of operation for AES.
Verilog
6
star
24

verilator_template

(Hopefully) simple template for a Verilator SystemVerilog project with a usable testbench
Verilog
6
star
25

ascon

Verilog implementation of the ASCON lightweight authenticated encryption and hashing algorithm
Verilog
6
star
26

gcm

Galois Couter Mode implementation in Verilog.
Verilog
5
star
27

rc4

An experimental RC4 hardware implementation with one cycle/iteration performance.
Verilog
5
star
28

aes_6502

My attempt at making a fast AES-128 implementation on MOS 6502
Verilog
5
star
29

aes_mask

Experimental core for performing masking of AES by generating noise.
Verilog
5
star
30

curve25519

Verilog 2001 of the Curve25519 elliptic curve based function.
Verilog
5
star
31

hmac

HMAC-SHA-256 in Verilog 2001
Verilog
4
star
32

xtea

Verilog implementation of the xtea block cipher
Verilog
4
star
33

avalanche_entropy

Entropy collector and provider for an external avalanche noise based entropy source.
Verilog
4
star
34

grain128

Hardware implementation of the Grain128AEAD stream cipher
Verilog
4
star
35

ccm

ccm mode hardware implementation
Verilog
4
star
36

view_rnd

A simple program for viewing random values as an image.
Python
3
star
37

vga

vga
Verilog
3
star
38

tracegen

A tool for generating synthetic traces with side-channel leakage.
Python
3
star
39

hc

Hardware implementation of the HC stream cipher.
Verilog
3
star
40

salsa20

Sals20 Stream Cipher core in Verilog
Verilog
3
star
41

r5

A simple Verilog implementation of RISC-V.
Verilog
3
star
42

extract_ev_data

Pure Python program used to extract EV data from Mozilla CA roots. Used to generate EV validation data in sslyze.
Python
3
star
43

fpga_eth_filter

FPGA based Ethernet traffic filter and manipulator for the TerasIC ETHERNET-HSMC Card
Verilog
3
star
44

bigmath

Project for testing and developing HW-implementations of integer operations. mult, mod, add, div etc.
Verilog
2
star
45

chaskey

Verilog implementation of the Chaskey lightweight message authentication code (MAC) function.
Verilog
2
star
46

online_tester

Online tester/monitor of random number generators. Based om AIS31 but modular.
Verilog
2
star
47

blake3

Hardware implementation of the Blake3 hash function
2
star
48

snow5

Hardware implementation of the SNOW-V stream cipher.
Verilog
2
star
49

aead_aes_siv_cmac

Hardware implementation of the AEAD_AES_SIV_CMAC
Verilog
2
star
50

fltfpga

FairLight FPGA demo board based on TerasIC G5C
Verilog
2
star
51

random_tools

A collection of tools used to analyze random number data files, extract entropy etc.
Python
2
star
52

tang_nano_rng

Implementation of a high quality random number generator on the Tang Nano FPGA board
2
star
53

coretest

Test structure for cores developed as part of the Cryptech Open HSM project
Verilog
2
star
54

siphash_6502

Implementation of the SipHash keyed hash function in MOS 6502 assembler
Assembly
2
star
55

Tweetnacl

Python implementation of the TweetNaCl cryptograhic library
Python
2
star
56

pyat88ck590

Python program to talk to the Atmel AT88CK590 Crypto Authentication Evaulation Kit.
Python
1
star
57

stanford_cryptography1

Solutions to programming problems and assignments in the Cryptography 1 course
1
star
58

keywrap

RFC 3394 keywrap cipher mode implemented in Verilog 2001.
Verilog
1
star
59

ubbefpga

Very simple HW design to test FPGA development using the Terasic DE0-Nano board
Verilog
1
star
60

blabla

Implementation of the BlaBla version of the ChaCha stream cipher
Verilog
1
star
61

vndecorrelator

A Verilog implementation of a von Neumann decorrelator
Verilog
1
star
62

robber_language

Hardware implementation of a decoder/encoder for the Robber language
Verilog
1
star
63

ca_prng

Cellular Automata based PRNG
Verilog
1
star
64

mkmif

interface to external master key memory.
Verilog
1
star
65

fpga_entropy

Test implementation of FPGA-internal entropy source.
Verilog
1
star
66

coretest_bp_entropy

Coretest system for testing the FPGA based entropy source by Berndt Paysan.
Verilog
1
star
67

verilogtest

Repo for test of HW implementations written in Verilog.
Verilog
1
star
68

rc4_6502

MOS 6502 implementation of the old RC4 stream cipher. Yes, it is broken.
1
star
69

advent_of_code_2019

Solutions to Adevent of Code 2019
Python
1
star
70

test_core

A very simple test core.
Verilog
1
star
71

huffman

Python implementation of Huffman encoding and decoding. Just for fun.
Python
1
star
72

coretest_test_core

The coretest module combined with the test_core as a test module.
Verilog
1
star
73

xchacha

Hardware implementation of the extended-nonce ChaCha stream cipher
Verilog
1
star
74

qarma

Verilog implementation of the lightweight block cipher QARMA
Verilog
1
star
75

ocb

Verilog implementation of the OCB authenticated encryption mode.
Verilog
1
star