secworks/chaskey secworks/chaskey

  • Stars
    star
    2
  • Language Verilog
  • License
    BSD 2-Clause "Sim...
  • Created over 4 years ago
  • Updated about 4 years ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
secworks/chaskey
github

secworks

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Verilog implementation of the Chaskey lightweight message authentication code (MAC) function.

More Repositories

1

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
Verilog
334
star
2

sha256

Hardware implementation of the SHA-256 cryptographic hash function
Verilog
316
star
3

trng

True Random Number Generator core implemented in Verilog.
Verilog
72
star
4

sha1

Verilog implementation of the SHA-1 cryptgraphic hash function
Verilog
51
star
5

chacha

Verilog 2001 implementation of the ChaCha stream cipher.
Verilog
38
star
6

sha512

Verilog implementation of the SHA-512 hash function.
Verilog
33
star
7

blake2

Hardware implementation of the blake2 hash function
Verilog
25
star
8

blake2s

Verilog implementation of the 32-bit version of the Blake2 hash function
Verilog
20
star
9

sha3

FIPS 202 compliant SHA-3 core in Verilog
Verilog
17
star
10

modexp

Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
Verilog
17
star
11

siphash

Hardware implementation of the SipHash short-inout PRF
Verilog
16
star
12

cmac

Implementation of the CMAC keyed hash function using AES as block cipher.
Verilog
12
star
13

chacha_testvectors

Generator and Internet Draft (I-D) documenting test vectors for the stream cipher ChaCha.
C
10
star
14

uart

A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.
Verilog
8
star
15

ChaCha20-Poly1305

Hardware implementation of the ChaCha20-Poly1305 AEAD construction
Verilog
8
star
16

gift

Hardware implementation of the GIFT-128 lightweight block cipher
Verilog
8
star
17

poly1305

Hardware implementation of the poly1305 message authentication function.
Verilog
8
star
18

rosc_entropy

Entropy source based on jitter between multiple, digital ring oscillators.
Verilog
7
star
19

6502

Verilog implementation of a MOS6502 compatible CPU core.
Verilog
7
star
20

prince

The Prince lightweight block cipher in Verilog.
Verilog
7
star
21

ed25519

ed25519 public key signature implemented in Verilog.
Verilog
7
star
22

md5

Hardware implementation of the hash function md5
Verilog
6
star
23

figaro

Implementation of the FiGaRO TRNG for FPGAs
Verilog
6
star
24

cbc

CBC block cipher mode of operation for AES.
Verilog
6
star
25

verilator_template

(Hopefully) simple template for a Verilator SystemVerilog project with a usable testbench
Verilog
6
star
26

ascon

Verilog implementation of the ASCON lightweight authenticated encryption and hashing algorithm
Verilog
6
star
27

gcm

Galois Couter Mode implementation in Verilog.
Verilog
5
star
28

rc4

An experimental RC4 hardware implementation with one cycle/iteration performance.
Verilog
5
star
29

aes_6502

My attempt at making a fast AES-128 implementation on MOS 6502
Verilog
5
star
30

aes_mask

Experimental core for performing masking of AES by generating noise.
Verilog
5
star
31

curve25519

Verilog 2001 of the Curve25519 elliptic curve based function.
Verilog
5
star
32

hmac

HMAC-SHA-256 in Verilog 2001
Verilog
4
star
33

xtea

Verilog implementation of the xtea block cipher
Verilog
4
star
34

avalanche_entropy

Entropy collector and provider for an external avalanche noise based entropy source.
Verilog
4
star
35

grain128

Hardware implementation of the Grain128AEAD stream cipher
Verilog
4
star
36

ccm

ccm mode hardware implementation
Verilog
4
star
37

view_rnd

A simple program for viewing random values as an image.
Python
3
star
38

vga

vga
Verilog
3
star
39

tracegen

A tool for generating synthetic traces with side-channel leakage.
Python
3
star
40

hc

Hardware implementation of the HC stream cipher.
Verilog
3
star
41

salsa20

Sals20 Stream Cipher core in Verilog
Verilog
3
star
42

r5

A simple Verilog implementation of RISC-V.
Verilog
3
star
43

extract_ev_data

Pure Python program used to extract EV data from Mozilla CA roots. Used to generate EV validation data in sslyze.
Python
3
star
44

fpga_eth_filter

FPGA based Ethernet traffic filter and manipulator for the TerasIC ETHERNET-HSMC Card
Verilog
3
star
45

bigmath

Project for testing and developing HW-implementations of integer operations. mult, mod, add, div etc.
Verilog
2
star
46

online_tester

Online tester/monitor of random number generators. Based om AIS31 but modular.
Verilog
2
star
47

blake3

Hardware implementation of the Blake3 hash function
2
star
48

snow5

Hardware implementation of the SNOW-V stream cipher.
Verilog
2
star
49

aead_aes_siv_cmac

Hardware implementation of the AEAD_AES_SIV_CMAC
Verilog
2
star
50

fltfpga

FairLight FPGA demo board based on TerasIC G5C
Verilog
2
star
51

random_tools

A collection of tools used to analyze random number data files, extract entropy etc.
Python
2
star
52

tang_nano_rng

Implementation of a high quality random number generator on the Tang Nano FPGA board
2
star
53

coretest

Test structure for cores developed as part of the Cryptech Open HSM project
Verilog
2
star
54

siphash_6502

Implementation of the SipHash keyed hash function in MOS 6502 assembler
Assembly
2
star
55

Tweetnacl

Python implementation of the TweetNaCl cryptograhic library
Python
2
star
56

pyat88ck590

Python program to talk to the Atmel AT88CK590 Crypto Authentication Evaulation Kit.
Python
1
star
57

stanford_cryptography1

Solutions to programming problems and assignments in the Cryptography 1 course
1
star
58

keywrap

RFC 3394 keywrap cipher mode implemented in Verilog 2001.
Verilog
1
star
59

ubbefpga

Very simple HW design to test FPGA development using the Terasic DE0-Nano board
Verilog
1
star
60

blabla

Implementation of the BlaBla version of the ChaCha stream cipher
Verilog
1
star
61

vndecorrelator

A Verilog implementation of a von Neumann decorrelator
Verilog
1
star
62

robber_language

Hardware implementation of a decoder/encoder for the Robber language
Verilog
1
star
63

ca_prng

Cellular Automata based PRNG
Verilog
1
star
64

mkmif

interface to external master key memory.
Verilog
1
star
65

fpga_entropy

Test implementation of FPGA-internal entropy source.
Verilog
1
star
66

coretest_bp_entropy

Coretest system for testing the FPGA based entropy source by Berndt Paysan.
Verilog
1
star
67

verilogtest

Repo for test of HW implementations written in Verilog.
Verilog
1
star
68

rc4_6502

MOS 6502 implementation of the old RC4 stream cipher. Yes, it is broken.
1
star
69

advent_of_code_2019

Solutions to Adevent of Code 2019
Python
1
star
70

test_core

A very simple test core.
Verilog
1
star
71

huffman

Python implementation of Huffman encoding and decoding. Just for fun.
Python
1
star
72

coretest_test_core

The coretest module combined with the test_core as a test module.
Verilog
1
star
73

xchacha

Hardware implementation of the extended-nonce ChaCha stream cipher
Verilog
1
star
74

qarma

Verilog implementation of the lightweight block cipher QARMA
Verilog
1
star
75

ocb

Verilog implementation of the OCB authenticated encryption mode.
Verilog
1
star