nicolavianello95/DLX nicolavianello95/DLX

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    2
  • Language VHDL
  • License
    GNU General Publi...
  • Created almost 5 years ago
  • Updated almost 5 years ago
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nicolavianello95/DLX
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nicolavianello95

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Repository Details

Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.

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