Discover nicolavianello95/RISC-V Open Source project

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Language Verilog
License
GNU General Publi...
Created over 4 years ago
Updated over 4 years ago

nicolavianello95

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Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.

FIR_filter

Modeling, Design and ASIC implementation of a tenth order FIR filter. This project has been developed in two versions: a basic one, and an improved one using 3-level unfolding and five stages pipeline.

VHDL

DLX

Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.

VHDL

register_file_windowing

VHDL register file with generic bitwidth, number of global register, number of windows, and number of registers per window.

VHDL

propeller_display

Design and realization of a "propeller display": A DC motor makes rotate a PCB, on which a row of LEDs is placed, at a frequency higher than that the human eye can perceive. A microcontroller detects the frequency using an infrared sensor and drives the LEDs in order to make a stable image appear.

parking_sensor

Design and prototyping of a parking sensor based on a microcontroller that manages four ultrasonic distance sensors and a temperature sensor, and according to these drives an LCD display and a buzzer. An FPGA allows to record all the measures and to send them to a PC if there is a request.

mult32_MBE_dadda

Design and VHDL description of a 32bit multiplier using a Modified Booth Encoding and a Dadda CSA tree.

VHDL

nicolavianello95/RISC-V

nicolavianello95

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