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RiSC-16
RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in pythonVerilog_projects
Some beginner projects using verilog HDL, along with some documentation on basic syntaxKalman_filter_carla
Kalman filter for self driving cars using imu and gnss data, acquired from the carla simulatorVerilog_comm
Implementation of several common digital communication protocols, to be used in FPGAs.RTL_Notes
Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notesUniversalRemote_ESP32
An IOT universal remote controller using the ESP32 microcontroller (ESP32-WROOM32 module), with firmware developed using ESP-IDFCordic_accelerator_projects
Project folders for CORDIC acceleratorCordic_accelerator
Accelerator IP for computing transcendental functions using CORDIC algorithmYosys_guide
A guide to exploring Yosys for logic synthesis.CMOS_Schmitt
Analog design and simulation of a CMOS Schmitt trigger using synopsys custom design compiler for the analog design hackathon by IITH and VSDQuintessence-StroboscopicWater
Code for stroboscopic water fall using solenoid valvesriscv
A RISC V processor with memory hierarchy with separate instruction and data cache (tested on FPGA with GCC compiled code)PyTorch_IEEE_2021
PLL_OSU180nm_VSD
Documentation of work done for PLL workshop for OSU 180nm node by VSD for VSD Open 2021LifeOnChip
Convay's Game of Life on silicon (Skywater130 using OpenLane)Love Open Source and this site? Check out how you can help us