Ashwin Rajesh (@Ashwin-Rajesh)
github

Ashwin-Rajesh

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  • Stars
    star
    47
  • Global Rank 356,388 (Top 13 %)
  • Followers 36
  • Following 56
  • Registered over 6 years ago
  • Most used languages
    Verilog     35.7 %
    SystemVerilog     21.4 %
    C++
         14.3 %
    Jupyter Notebook
         14.3 %
    HTML
         7.1 %
    SourcePawn     7.1 %
  • Location ๐Ÿ‡ฎ๐Ÿ‡ณ India
  • Country Total Rank 21,220
  • Country Ranking
    SystemVerilog     8
    SourcePawn     18
    Verilog     33
    C++
         4,694
    Jupyter Notebook
         5,708

Top repositories

1

RiSC-16

RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python
SystemVerilog
10
star
2

Verilog_projects

Some beginner projects using verilog HDL, along with some documentation on basic syntax
Verilog
8
star
3

Kalman_filter_carla

Kalman filter for self driving cars using imu and gnss data, acquired from the carla simulator
Jupyter Notebook
5
star
4

Verilog_comm

Implementation of several common digital communication protocols, to be used in FPGAs.
Verilog
5
star
5

RTL_Notes

Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notes
Verilog
5
star
6

UniversalRemote_ESP32

An IOT universal remote controller using the ESP32 microcontroller (ESP32-WROOM32 module), with firmware developed using ESP-IDF
C++
2
star
7

Cordic_accelerator_projects

Project folders for CORDIC accelerator
HTML
2
star
8

Cordic_accelerator

Accelerator IP for computing transcendental functions using CORDIC algorithm
SystemVerilog
2
star
9

Yosys_guide

A guide to exploring Yosys for logic synthesis.
1
star
10

CMOS_Schmitt

Analog design and simulation of a CMOS Schmitt trigger using synopsys custom design compiler for the analog design hackathon by IITH and VSD
1
star
11

Quintessence-StroboscopicWater

Code for stroboscopic water fall using solenoid valves
C++
1
star
12

riscv

A RISC V processor with memory hierarchy with separate instruction and data cache (tested on FPGA with GCC compiled code)
Verilog
1
star
13

fpga_functiongen

A simple function generator for square, sine (using CORDIC) and sawtooth waveforms on the basys3 board (with PMOD DAC)
SystemVerilog
1
star
14

PyTorch_IEEE_2021

Jupyter Notebook
1
star
15

PLL_OSU180nm_VSD

Documentation of work done for PLL workshop for OSU 180nm node by VSD for VSD Open 2021
SourcePawn
1
star
16

LifeOnChip

Convay's Game of Life on silicon (Skywater130 using OpenLane)
Verilog
1
star