Discover Ashwin-Rajesh/RiSC-16 Open Source project

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Rank 1,807,489 (Top 36 %)
Language SystemVerilog
License
MIT License
Created almost 3 years ago
Updated almost 3 years ago

Ashwin-Rajesh

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RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python

Verilog_projects

Some beginner projects using verilog HDL, along with some documentation on basic syntax

Verilog

Kalman_filter_carla

Kalman filter for self driving cars using imu and gnss data, acquired from the carla simulator

Jupyter Notebook

Verilog_comm

Implementation of several common digital communication protocols, to be used in FPGAs.

Verilog

RTL_Notes

Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notes

Verilog

UniversalRemote_ESP32

An IOT universal remote controller using the ESP32 microcontroller (ESP32-WROOM32 module), with firmware developed using ESP-IDF

C++

Cordic_accelerator_projects

Project folders for CORDIC accelerator

HTML

Cordic_accelerator

Accelerator IP for computing transcendental functions using CORDIC algorithm

SystemVerilog

Yosys_guide

A guide to exploring Yosys for logic synthesis.

CMOS_Schmitt

Analog design and simulation of a CMOS Schmitt trigger using synopsys custom design compiler for the analog design hackathon by IITH and VSD

Quintessence-StroboscopicWater

Code for stroboscopic water fall using solenoid valves

C++

riscv

A RISC V processor with memory hierarchy with separate instruction and data cache (tested on FPGA with GCC compiled code)

Verilog

fpga_functiongen

A simple function generator for square, sine (using CORDIC) and sawtooth waveforms on the basys3 board (with PMOD DAC)

SystemVerilog

PyTorch_IEEE_2021

Jupyter Notebook

PLL_OSU180nm_VSD

Documentation of work done for PLL workshop for OSU 180nm node by VSD for VSD Open 2021

SourcePawn

LifeOnChip

Convay's Game of Life on silicon (Skywater130 using OpenLane)

Verilog

Ashwin-Rajesh/RiSC-16

Ashwin-Rajesh

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