Yiğit Süoğlu (@suoglu)
github

suoglu

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  • Stars
    star
    112
  • Global Rank 190,952 (Top 7 %)
  • Followers 22
  • Following 3
  • Registered over 8 years ago
  • Most used languages
    Verilog     77.8 %
    Tcl     16.7 %
    Python
         5.6 %
  • Location 🇩🇪 Germany
  • Country Total Rank 11,444
  • Country Ranking
    Verilog     6
    Tcl     40

Top repositories

1

Fixed-Floating-Point-Adder-Multiplier

16-bit Adder Multiplier hardware on Digilent Basys 3
Verilog
60
star
2

Carry-Save-Multiplier

Parameterized and 4-bit carry save multiplier design
Verilog
5
star
3

Pmod

Collection of simple interfaces for Digilent Pmods
Verilog
5
star
4

IR-Transreceiver

Encoder and decoder modules for infrared receivers, transmitters and remotes
Verilog
5
star
5

Integer-Multiplier-Hardware-Parameterized

Source code for pure combinational 16 bit integer multiplier hardware
Verilog
5
star
6

Digital_Clock

Verilog code for a digital clock
Verilog
4
star
7

Queue-Management-System

Simple queue management system
Verilog
4
star
8

Verilog-Utilty-Modules

Collection of utility modules written in Verilog
Verilog
3
star
9

HC-SR04

Verilog interface for HC-SR04 Ultrasonic Ranging Module
Verilog
3
star
10

Divider

Hardware integer divider module
Tcl
3
star
11

VSC-Snippets

Some snippets for Verilog HDL to be used in VS Code
3
star
12

xorshiftPlus

Pseudorandom number generator
Verilog
3
star
13

UART-Tool

Serial communication tool written in Python 3
Python
2
star
14

MCP4725

Interface module for MCP4725 DAC
Verilog
2
star
15

STC

Sensitivity Time Control function implementation with a simple sea clutter generator and radar interface
Verilog
1
star
16

Sequential-CRC-Generator

Pair of modules to calculate crc values sequentially
Verilog
1
star
17

AXIS-Split

Splits one AXI-Stream transmission to two.
Tcl
1
star
18

AXI-GPIO

Custom AXI GPIO core with up to 32 input and 32 output ports
Tcl
1
star
19

Simple-UART

Set of simple modules to communicate via UART
Verilog
1
star