yrsltn/Integrated-Circuit-Desing-in-Verilog

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Language Verilog
Created about 4 years ago
Updated about 3 years ago

yrsltn/Integrated-Circuit-Desing-in-Verilog

yrsltn

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To design a circuit to find the maximum number among a given set of numbers, simulate it and finally implement.

Schedule-generator-for-a-school-

The broad aim of the project is to develop a C++ programme which will generate automated time table for a university