Discover ultraembedded/core_sdram_axi4 Open Source project

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Rank 509,601 (Top 11 %)
Language
C++
License
GNU General Publi...
Created over 5 years ago
Updated over 5 years ago

ultraembedded

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SDRAM controller with AXI4 interface

riscv

RISC-V CPU Core (RV32IM)

Verilog

984

biriscv

32-bit Superscalar RISC-V CPU

Verilog

701

cores

Various HDL (Verilog) IP Cores

Verilog

598

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

Verilog

260

FPGAmp

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

237

core_jpeg

High throughput JPEG decoder in Verilog for FPGA

Verilog

166

openlogicbit

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

Verilog

core_usb_host

Basic USB 1.1 Host Controller for small FPGAs

riscv_soc

Basic RISC-V Test SoC

Verilog

exactstep

Instruction set simulator for RISC-V, MIPS and ARM-v6m

C++

core_ft60x_axi

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

C++

libhelix-mp3

Fixed-point MP3 decoder (RISC-V port)

core_dvi_framebuffer

Minimal DVI / HDMI Framebuffer

Verilog

core_audio

Audio controller (I2S, SPDIF, DAC)

Verilog

core_usb_cdc

Basic USB-CDC device core (Verilog)

Verilog

usb_sniffer

High Speed USB 2.0 capture device based on miniSpartan6+

core_soc

Basic Peripheral SoC (SPI, GPIO, Timer, UART)

Verilog

core_uriscv

Another tiny RISC-V implementation

Verilog

fat_io_lib

Small footprint, low dependency, C code implementation of a FAT16 & FAT32 driver.

usb2sniffer

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)

Verilog

core_dbg_bridge

UART -> AXI Bridge

Verilog

riscv-linux-boot

Trivial RISC-V Linux binary bootloader

core_usb_fs_phy

USB Full Speed PHY

Verilog

core_spiflash

SPI-Flash XIP Interface (Verilog)

Verilog

core_usb_bridge

USB -> AXI Debug Bridge

Verilog

core_usb_uart

USB serial device (CDC-ACM)

Verilog

core_jpeg_decoder

HW JPEG decoder wrapper with AXI-4 DMA

Verilog

core_axi_cache

128KB AXI cache (32-bit in, 256-bit out)

Verilog

riscv_sbc

A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.

Verilog

fpga_test_soc

A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)

core_enet

Ethernet MAC 10/100 Mbps

Verilog

core_mmc

MMC (and derivative standards) host controller

Verilog

minispartan6-audio

miniSpartan6+ (Spartan6) FPGA based MP3 Player

Verilog

core_ftdi_bridge

FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge

Verilog

core_ulpi_wrapper

ULPI Link Wrapper (USB Phy Interface)

C++

core_usb_sniffer

USB capture IP

Verilog

riscv32_linux_from_scratch

RISC-V 32-bit Linux From Scratch

Makefile

librtos

Very basic real time operating system for embedded systems...

ecpix-5

Projects for the ECPiX-5 - a ECP5 FPGA board.

Verilog

minispartan6

Projects for the Scarab Minispartan6+ FPGA board

VHDL

core_ram_tester

AXI-4 RAM Tester Component

Verilog

altor32

AltOr32 - Alternative Lightweight OpenRisc CPU

Verilog

armv6m-sim

Simple instruction set simulator for ARMv6-M (Cortex M0)

C++

core_mpx

MPX is a open-source CPU which can execute code compiled for MIPS-I ISA

Verilog

xc6_bus_pirate

XC6 Bus Pirate (FPGA based multi-tool)

Verilog

orangecrab

Test projects for the OrangeCrab ECP5 FPGA board

Verilog

ecpix5-test

Test code / bitstreams for the LambdaConcept ECPIX-5 FPGA board

Verilog

riscv-sw-test

C++

riscv-linux-prebuilt

RISC-V Linux prebuilt images

embedded_httpd

Embedded HTTP Server

rp2040_blinky

Simple blinky example for the RP2040 that does not require cmake

C++

ultraembedded/core_sdram_axi4

ultraembedded

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