@ultraembedded
github

ultraembedded

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  • Stars
    star
    4,497
  • Global Rank 6,163 (Top 0.3 %)
  • Followers 1,016
  • Following 4
  • Registered over 10 years ago
  • Most used languages
    Verilog     64.7 %
    C
         17.6 %
    C++
         13.7 %
    VHDL     2.0 %
    Makefile     2.0 %
  • Location πŸ‡¬πŸ‡§ United Kingdom
  • Country Total Rank 314
  • Country Ranking
    Verilog     1
    VHDL     31
    C
         100
    Makefile     116
    C++
         248

Top repositories

1

riscv

RISC-V CPU Core (RV32IM)
Verilog
984
star
2

biriscv

32-bit Superscalar RISC-V CPU
Verilog
701
star
3

cores

Various HDL (Verilog) IP Cores
Verilog
598
star
4

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs
Verilog
260
star
5

FPGAmp

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
C
237
star
6

core_jpeg

High throughput JPEG decoder in Verilog for FPGA
Verilog
166
star
7

openlogicbit

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
Verilog
87
star
8

core_usb_host

Basic USB 1.1 Host Controller for small FPGAs
C
77
star
9

riscv_soc

Basic RISC-V Test SoC
Verilog
76
star
10

exactstep

Instruction set simulator for RISC-V, MIPS and ARM-v6m
C++
74
star
11

core_ft60x_axi

FTDI FT600 SuperSpeed USB3.0 to AXI bus master
C++
73
star
12

libhelix-mp3

Fixed-point MP3 decoder (RISC-V port)
C
66
star
13

core_dvi_framebuffer

Minimal DVI / HDMI Framebuffer
Verilog
65
star
14

core_audio

Audio controller (I2S, SPDIF, DAC)
Verilog
64
star
15

core_usb_cdc

Basic USB-CDC device core (Verilog)
Verilog
61
star
16

core_sdram_axi4

SDRAM controller with AXI4 interface
C++
59
star
17

usb_sniffer

High Speed USB 2.0 capture device based on miniSpartan6+
C
56
star
18

core_soc

Basic Peripheral SoC (SPI, GPIO, Timer, UART)
Verilog
51
star
19

core_uriscv

Another tiny RISC-V implementation
Verilog
49
star
20

fat_io_lib

Small footprint, low dependency, C code implementation of a FAT16 & FAT32 driver.
C
48
star
21

usb2sniffer

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
Verilog
42
star
22

core_dbg_bridge

UART -> AXI Bridge
Verilog
41
star
23

riscv-linux-boot

Trivial RISC-V Linux binary bootloader
C
38
star
24

core_usb_fs_phy

USB Full Speed PHY
Verilog
35
star
25

core_spiflash

SPI-Flash XIP Interface (Verilog)
Verilog
33
star
26

core_usb_bridge

USB -> AXI Debug Bridge
Verilog
32
star
27

core_usb_uart

USB serial device (CDC-ACM)
Verilog
27
star
28

core_jpeg_decoder

HW JPEG decoder wrapper with AXI-4 DMA
Verilog
24
star
29

core_axi_cache

128KB AXI cache (32-bit in, 256-bit out)
Verilog
24
star
30

riscv_sbc

A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
Verilog
24
star
31

fpga_test_soc

A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
C
22
star
32

core_enet

Ethernet MAC 10/100 Mbps
Verilog
21
star
33

core_mmc

MMC (and derivative standards) host controller
Verilog
21
star
34

minispartan6-audio

miniSpartan6+ (Spartan6) FPGA based MP3 Player
Verilog
21
star
35

core_ftdi_bridge

FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
Verilog
20
star
36

core_ulpi_wrapper

ULPI Link Wrapper (USB Phy Interface)
C++
19
star
37

core_usb_sniffer

USB capture IP
Verilog
18
star
38

riscv32_linux_from_scratch

RISC-V 32-bit Linux From Scratch
Makefile
18
star
39

librtos

Very basic real time operating system for embedded systems...
C
14
star
40

ecpix-5

Projects for the ECPiX-5 - a ECP5 FPGA board.
Verilog
12
star
41

minispartan6

Projects for the Scarab Minispartan6+ FPGA board
VHDL
12
star
42

core_ram_tester

AXI-4 RAM Tester Component
Verilog
11
star
43

altor32

AltOr32 - Alternative Lightweight OpenRisc CPU
Verilog
11
star
44

armv6m-sim

Simple instruction set simulator for ARMv6-M (Cortex M0)
C++
10
star
45

core_mpx

MPX is a open-source CPU which can execute code compiled for MIPS-I ISA
Verilog
9
star
46

xc6_bus_pirate

XC6 Bus Pirate (FPGA based multi-tool)
Verilog
7
star
47

orangecrab

Test projects for the OrangeCrab ECP5 FPGA board
Verilog
6
star
48

ecpix5-test

Test code / bitstreams for the LambdaConcept ECPIX-5 FPGA board
Verilog
6
star
49

riscv-sw-test

C++
5
star
50

riscv-linux-prebuilt

RISC-V Linux prebuilt images
5
star
51

embedded_httpd

Embedded HTTP Server
C
3
star
52

rp2040_blinky

Simple blinky example for the RP2040 that does not require cmake
C++
3
star